Early Career - GPU Top Level Physical Design Engineer

. Apple (UK) Limited; Cambridge; On-site; GBP 90,000 - 120,000; Full time

Job summary

Apple (UK) Limited in Cambridge is seeking a GPU Top-Level Physical Design engineer to drive full chip implementation from netlist to tapeout. You will work with the Front-End team to understand RTL and push physical design early in the design cycle, developing methodologies and best‑known methods for best-in-class GPU design.

You will lead place and route at the top level, develop PD guidelines, oversee progress, and coordinate with cross‑functional teams to meet project milestones.

Qualifications

• BSc or MSc in Electrical Engineering with relevant experience.
• ASIC integration including Floorplanning, Clock and Power distribution, IO planning and IP integration.

Responsibilities

• Implement chip design from netlist to tapeout.
• Work with FE team to translate RTL into physical design early in the cycle.
• Develop PD guidelines and checklists and drive execution.
• Be the focal point for place and route at the top level.
• Coordinate PD needs with cross‑functional teams to meet goals.

Skills

Floorplanning

Clock distribution

Power distribution

IO planning

IP integration

Physical design

Placement and routing

Timing convergence

Education

BSc/MSc in EE

Tools

Floorplanning tools

P&R flows

Timing verification

Physical Design Verification

Job description

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU. You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration. Join us!

DescriptionAs a GPU Top Level Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the physical design team, as you develop methodologies and "best known methods" that will enable best-in-class GPU design. You will develop PD guidelines and checklists, drive execution, and supervise progress. Be the focal point for place and route integration at the top level. You will need to communicate and drive the needs of PD with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Minimum Qualifications

• Minimum of BSc/MSc in EE and some relevant experience.
• Familiar with ASIC integration including Floorplanning, Clock and Power distribution, global signal planning, I/O planning and hard IP integration.

Preferred Qualifications

• Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.
• Experience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.
• Experience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.
• Familiar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.
• Proven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs.
• Understanding of GPU architecture and design units.
• Experience with hierarchical design approach, top-down design, budgeting, timing and physical convergence.
• Experience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows.