Early Career - Front-End Implementation Engineer (Synthesis)

Apple Inc.; Greater London; On-site; GBP 65,000 - 90,000; Full time

Job summary

Apple Inc. in London is seeking an RTL engineer to work on PPA optimisation of the netlist for Apple Silicon GPUs. You will collaborate with RTL and Physical design teams to improve netlist quality milestones and push forward advanced GPU products.

The role requires a BSc in EE and experience with Verilog or SystemVerilog and scripting; knowledge of physical synthesis, timing analysis, and DFT is preferred. Apple values inclusive hiring and accessibility.

Qualifications

• BSc in EE required.
• Experience with Verilog or SystemVerilog and scripting.
• Understanding of physical synthesis and PPA optimisation techniques.

Responsibilities

• PPA optimisation of the netlist and collaboration with RTL and Physical design teams.
• Deliver key netlist quality milestones for partitions and improve methodologies.
• Contribute to delivering GPUs for Apple Silicon and engage with IP teams across sites.

Skills

Verilog

SystemVerilog

PPA optimisation

RTL design

Scripting

Education

BSc in EE

Job description

Selection changes the language of the page/content

Imagine working in a team where the only limits are the laws of physics and your imagination.At Apple, phenomenal ideas have a way of becoming phenomenal products and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices.Join the team that optimises and delivers world class GPUs into Apple Silicon. As part of the GPU Front End Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.Join us!

Description

Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPUs for the best consumer products.If you’re ready to help chart the future of Apple Silicon, we would love to talk to you.

Minimum Qualifications

• Minimum of BSc in EE.
• Exposure in Verilog and/or System Verilog and scripting languages.
• General understanding of physical synthesis, including logic and PPA optimisation techniques.

Preferred Qualifications

• Understanding and application of physical design and static timing analysis principles.
• Familiarity with DFT insertion.
• Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
• Ability to analyze critical paths and guide RTL designs to efficient solutions.
• Collaborate optimally with IP teams spanning multiple sites.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more

At Apple, we believe accessibility is a fundamental human right. You’ll find that idea reflected in everything here — in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
Learn about accessibility in Apple’s workplace