Early Career - Front-End Implementation Engineer (Synthesis)

Lex; Greater London; On-site; GBP 70,000 - 110,000; Full time

Job summary

Apple is seeking a GPU Front End Engineer in the UK to optimize PPA of the netlist and collaborate across RTL and Physical design teams. You will deliver netlist quality milestones and contribute to the evolution of our GPU methodologies to power consumer products.

Role involves crafting GPUs for Apple Silicon, with opportunities to influence design across multi-site IP teams. Strong Verilog/SystemVerilog and scripting experience valued.

Qualifications

• BSc in EE required.
• Exposure to Verilog/SystemVerilog and scripting languages.
• Understanding of physical synthesis and PPA optimization.

Responsibilities

• PPA optimisation of the netlist, collaborating with RTL and Physical design teams.
• Deliver key netlist quality milestones for your partition.
• Understand and improve current methodologies to deliver outstanding GPUs for Apple Silicon.

Skills

Verilog/SystemVerilog

Scripting languages

Physical synthesis / PPA

RTL & Gate‑Level linting

DFT insertion

UPF / multi-clock domain

Critical path analysis

IP collaboration

Education

BSc in EE

Job description

Summary

Imagine working in a team where the only limits are the laws of physics and your imagination. At Apple, phenomenal ideas have a way of becoming phenomenal products and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The same real passion for innovation that goes into our products also applies to our practices. Join the team that optimises and delivers world class GPUs into Apple Silicon. As part of the GPU Front End Implementation team, you’ll be responsible for crafting and building a GPU that enriches the lives of millions of people every day.

Description

Candidates will be responsible for PPA optimisation of the netlist, working collaboratively with the RTL and Physical design teams. You will also deliver key netlist quality milestones for your partition and be involved in understanding and improving our current methodologies. Through this collaboration, you will deliver the outstanding GPUs for the best consumer products.

Minimum Qualifications

• Minimum of BSc in EE.
• Exposure in Verilog and/or System Verilog and scripting languages.
• General understanding of physical synthesis, including logic and PPA optimisation techniques.

Preferred Qualifications

• Understanding and application of physical design and static timing analysis principles.
• Familiarity with DFT insertion.
• Familiarity with reset domain, multi-clock domain, multi-power domain (UPF), linting tools and concepts across RTL and Gate-Level.
• Ability to analyze critical paths and guide RTL designs to efficient solutions.
• Collaborate optimally with IP teams spanning multiple sites.

At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more

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Role Number: 200688187-2114