Formal Verification Engineer: Hardware IPs Validation

. Apple (UK) Limited; Greater London; On-site; GBP 65,000 - 90,000; Full time

Job summary

Apple in London seeks a Design Verification Engineer to drive end-to-end verification strategy, from specifications to sign-off. You will formalize properties, execute proofs, and document verification methodology, interfacing with multiple teams across the AMS IP portfolio.

The role emphasizes strong mathematical acumen, experience with Verilog/VHDL, scripting (Perl/Python), and collaboration with international teams to deliver high-quality hardware models.

Qualifications

• Currently enrolled in Computer Science or equivalent.
• Knowledge of formal verification techniques.
• Knowledge of Verilog and/or VHDL.
• Passionate about mathematics, and good mathematical/analytical sense.
• Scripting language knowledge (Perl/Python).
• Good written and verbal communication skills.
• Experience in working with international teams.

Responsibilities

• Define comprehensive property sets for functional coverage of hardware models.
• Formalize verification properties using SVA.
• Execute formal proofs and analyze convergence behavior (accuracy VS execution time).
• Document methodology and best practices for the verification flow.

Skills

Communication skills

Team collaboration

Mathematics/analytical thinking

Currently enrolled in CS

Education

Master's in CS

Bachelor's in CS

Tools

Verilog

VHDL

Perl

Python

Job description

Apple in London seeks a Design Verification Engineer to drive end-to-end verification strategy, from specifications to sign-off. You will formalize properties, execute proofs, and document verification methodology, interfacing with multiple teams across the AMS IP portfolio.

The role emphasizes strong mathematical acumen, experience with Verilog/VHDL, scripting (Perl/Python), and collaboration with international teams to deliver high-quality hardware models.