Experienced AMS Design Verification Engineer

. Apple (UK) Limited; Greater London; On-site; GBP 75,000 - 110,000; Full time

Job summary

Apple in London invites a Design Verification Engineer to join the Advanced Technology group. You will drive pre-silicon verification for mixed-signal designs, building self-checking environments and writing tests and assertions in SystemVerilog/UVM.

You will collaborate with Analog and Digital Design teams to enable bug-free tape-outs, perform power and timing analyses, and push verification innovations in a fast-paced environment at Apple.

Qualifications

• Knowledge of SystemVerilog and UVM for advanced verification.
• Hands-on experience with constrained random verification environments.
• Basic design background to interpret verification results.
• Knowledge of OOP concepts.
• Proficiency in English language is required.

Responsibilities

• Create self-checking verification environments for mixed-signal designs.
• Develop test scenarios and assertions to enable bug-free tape-outs.
• Collaborate with Analog and Digital Design engineers across teams.

Skills

SystemVerilog

UVM

Constrained random

OOP

English proficiency

Education

Master's degree or PhD in Electrical/Computer Engineering

Tools

C++

Python

Verilog

FPGA emulation

Job description

At Apple, we work daily to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a forward-thinking and creative Design Verification Engineer. As a member of our Advanced Technology group, you will have the rare and rewarding opportunity to craft upcoming products, which will delight and encourage millions of Apple's customers every single day. Do your life's best work here at Apple! This role is for a Design Verification Engineer who will enable bug-free first silicon for the mixed-signal designs in our NEW London team. The responsibilities include all phases of pre-silicon verification, including but not limited to: construction of verification environments, coding of test scenarios and assertions, and close collaboration with Analog and Digital Design engineers.

DescriptionDefinition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library. The responsibility spans from concept discussions, verification strategy definition and execution of the verification tasks to ensure bug-free tape-outs. The AMS DV engineer goes beyond standard verification techniques and include:

• performance-based analysis
• power related analysis and scenario design for early power estimation
• deliveries of tests for design and test engineering teams
• gate-level verification (power and timing)
• lab bring-up support

A significant part of the AMS DV team focuses on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality. Looking forward and establishing cutting edge concepts and methods to support them are part of the AMS DV team's DNA.

Minimum Qualifications

• Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
• Hands-on experience with constrained random verification environments
• Basic design background in support of verification results analysis
• Knowledge of Object Oriented Programming (OOP)
• Proficiency in English language is required

Preferred Qualifications

• Master's degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
• Experience in AI/ML is desired
• Hands-on experience with Assertion Based Verification
• Familiarity with system design using C++, Python or Verilog
• Familiarity with FPGA emulation platforms

Apple is an Equal Opportunity Employer that is committed to inclusion and diversity. We also take affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities. Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants.