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Apple Inc. in London design center is seeking a Design Verification Engineer intern to contribute to the Formal Verification Framework for Hardware IPs Validation.
The role involves defining the verification strategy, executing formal proofs, and collaborating with international teams to ensure high-quality hardware models. Ideal candidates are Computer Science students with knowledge of Verilog/VHDL, SVA, and scripting skills, available for at least 6 months.
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Join a rapidly growing team at our London design center. At Apple, new ideas and complex challenges have a way of becoming phenomenal products, services, and customer experiences very quickly.The AMS IP team owns a wide portfolio of IPs & complete subsystems going to all the Apple products. In this context the Design Verification Engineer will have to interface with many different teams at Apple and build knowledge of many chips & platforms in order to bring system-level understanding into the verification flow. The responsibility goes end-to-end: starting at the specification level, defining the verification strategy & plan, executing the verification, doing performance analysis and handling all the different quality metrics to signoff the verification.
Define comprehensive property sets for functional coverage of hardware modelsFormalize verification properties using SVAExecute formal proofs and analyze convergence behavior (accuracy VS execution time)Document methodology and best practices for the verification flow
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