AMS Design Verification Engineer – SystemVerilog/UVM

. Apple (UK) Limited; Greater London; On-site; GBP 75,000 - 110,000; Full time

Job summary

Apple in London invites a Design Verification Engineer to join the Advanced Technology group. You will drive pre-silicon verification for mixed-signal designs, building self-checking environments and writing tests and assertions in SystemVerilog/UVM.

You will collaborate with Analog and Digital Design teams to enable bug-free tape-outs, perform power and timing analyses, and push verification innovations in a fast-paced environment at Apple.

Qualifications

• Knowledge of SystemVerilog and UVM for advanced verification.
• Hands-on experience with constrained random verification environments.
• Basic design background to interpret verification results.
• Knowledge of OOP concepts.
• Proficiency in English language is required.

Responsibilities

• Create self-checking verification environments for mixed-signal designs.
• Develop test scenarios and assertions to enable bug-free tape-outs.
• Collaborate with Analog and Digital Design engineers across teams.

Skills

SystemVerilog

UVM

Constrained random

OOP

English proficiency

Education

Master's degree or PhD in Electrical/Computer Engineering

Tools

C++

Python

Verilog

FPGA emulation

Job description

Apple in London invites a Design Verification Engineer to join the Advanced Technology group. You will drive pre-silicon verification for mixed-signal designs, building self-checking environments and writing tests and assertions in SystemVerilog/UVM.

You will collaborate with Analog and Digital Design teams to enable bug-free tape-outs, perform power and timing analyses, and push verification innovations in a fast-paced environment at Apple.