Formal Verification Intern - Hardware IPs

Apple Inc.; Greater London; On-site; GBP 16,000 - 23,000; Part time

Job summary

Apple Inc. in London design center is seeking a Design Verification Engineer intern to contribute to the Formal Verification Framework for Hardware IPs Validation.

The role involves defining the verification strategy, executing formal proofs, and collaborating with international teams to ensure high-quality hardware models. Ideal candidates are Computer Science students with knowledge of Verilog/VHDL, SVA, and scripting skills, available for at least 6 months.

Qualifications

• Currently enrolled in Computer Science or equivalent.
• Knowledge of formal verification techniques.
• Knowledge of Verilog and/or VHDL.
• Scripting languages (Perl/Python).
• Good written and verbal communication skills.
• Experience in working with international teams.

Responsibilities

• Develop comprehensive property sets to achieve functional coverage of hardware models.
• Formalize properties in SVA and execute formal proofs.
• Extend verification framework to higher levels for system verification.

Skills

Formal verification

Verilog/VHDL

Scripting

Communication skills

International teamwork

Education

Bachelor’s or Master’s in Computer Science

Job description

Apple Inc. in London design center is seeking a Design Verification Engineer intern to contribute to the Formal Verification Framework for Hardware IPs Validation.

The role involves defining the verification strategy, executing formal proofs, and collaborating with international teams to ensure high-quality hardware models. Ideal candidates are Computer Science students with knowledge of Verilog/VHDL, SVA, and scripting skills, available for at least 6 months.