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Apple in Swindon is seeking a driven Design Verification Engineer to enable bug-free silicon for mixed-signal designs. You will develop verification plans, build test benches, and collaborate with Digital and Analog teams to ensure robust pre-silicon validation.
The role requires strong SystemVerilog and UVM skills, experience with constrained random environments, and a degree in CS or EE. Excellent communication and teamwork are essential to help Apple deliver high-quality products to customers
At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a driven and highly committed Design Verification Engineer. As a member of our multifaceted group, you will have the unique opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every day. We are looking for a Design Verification Engineer in our team, who will enable bug-free first silicon for our mixed-signal designs, in close collaboration with Digital and Analog Design engineers. The responsibilities include all phases of pre-silicon verification including, establishing design verification methodology and test-plan development. Additional responsibilities will include verification environment development, such as stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
In this role you will develop verification plans in coordination with design leads and architects. You'll be responsible for building and maintaining verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Build functional coverage points, analyze coverage, and improve test environment to target coverage holes. Craft automated verification flows for block and chip level verification. Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM/VVM), and logic simulators to verify complex designs. Work with other block and core level engineers to ensure a flawless verification flow.
At Apple, we're not all the same. And that's our greatest strength. We draw on the differences in who we are, what we've experienced and how we think. Because to create products that serve everyone, we believe in including everyone. Therefore, we are committed to treating all applicants fairly and equally. As a registered Disability Confident employer, we will work with applicants to make any reasonable accommodations. Apple will consider for employment all qualified applicants with criminal backgrounds in a manner consistent with applicable law. Learn more
At Apple, we believe accessibility is a fundamental human right. You'll find that idea reflected in everything here - in our culture, our benefits and our digital tools. By welcoming as many perspectives as possible, we help you build a career where you feel like you belong.
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Role Number: 200690694-5490