SRAM Design & Yield Intern — Advanced IC Research

Cadence; Valbonne; On-site; EUR 12,000 - 18,000; Full time

Job summary

Cadence is seeking a final-year engineering or Master’s student for a 6-month internship in Sophia-Antipolis, France. You will work on SRAM design, self-timing optimization, and memory compiler technologies, contributing to state-of-the-art embedded memory IP.

The role offers hands-on experience in hardware-aware software development, circuit simulation, and variability analysis within a leading EDA and IP company.

Qualifications

• Final-year engineering student or Master’s candidate in microelectronics, electronics, computer engineering, computer science, applied physics or data science.
• Curiosity, enthusiasm and a desire to learn are essential.

Responsibilities

• Analyze SRAM self-timing paths under advanced process variations.
• Study and benchmark timing tracking methodologies.
• Develop simulation and evaluation methodologies.
• Propose architectural improvements to improve performance while preserving robustness.
• Analyze SRAM yield under statistical process variations and explore yield allocation strategies.

Skills

Microelectronics

Electrical Engineering

Data Science

Computer Science

Applied Physics

Education

Final-year engineering student

Master’s student

Equivalent qualification

Tools

Circuit simulation tools

Job description

Cadence is seeking a final-year engineering or Master’s student for a 6-month internship in Sophia-Antipolis, France. You will work on SRAM design, self-timing optimization, and memory compiler technologies, contributing to state-of-the-art embedded memory IP.

The role offers hands-on experience in hardware-aware software development, circuit simulation, and variability analysis within a leading EDA and IP company.