Intern AFG Memoire

Cadence; Valbonne; Presencial; EUR 12.000 - 18.000; Jornada completa

Descripción de la vacante

Cadence is seeking a final-year engineering or Master’s student for a 6-month internship in Sophia-Antipolis, France. You will work on SRAM design, self-timing optimization, and memory compiler technologies, contributing to state-of-the-art embedded memory IP.

The role offers hands-on experience in hardware-aware software development, circuit simulation, and variability analysis within a leading EDA and IP company.

Formación

• Final-year engineering student or Master’s candidate in microelectronics, electronics, computer engineering, computer science, applied physics or data science.
• Curiosity, enthusiasm and a desire to learn are essential.

Responsabilidades

• Analyze SRAM self-timing paths under advanced process variations.
• Study and benchmark timing tracking methodologies.
• Develop simulation and evaluation methodologies.
• Propose architectural improvements to improve performance while preserving robustness.
• Analyze SRAM yield under statistical process variations and explore yield allocation strategies.

Conocimientos

Microelectronics

Electrical Engineering

Data Science

Computer Science

Applied Physics

Educación

Final-year engineering student

Master’s student

Equivalent qualification

Herramientas

Circuit simulation tools

Descripción del empleo

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace , industrial and health.

We are looking for a final-year engineering or Master's student, or pursuing an equivalent qualification, in microelectronics, electronics, computer engineering, computer science, applied physics, data science, or a related discipline

Title: Intern

Location : Sophia-Antipolis, France

Duration : 6 months

From : early Q1 2027

We are considering three possible internship topics and expect to select for only one of them. When applying, please indicate the topic that best matches your interests and experience. You may also mention if you would be interested in extended topic.

• Internship 1: Advanced SRAM Design and Self-Timing Optimization
• Internship 2: Statistical Yield Optimization for Next-Generation SRAM Memories
• Internship 3: Power Characterization Methodology for Memory Compilers

What Matters Most

Curiosity, enthusiasm, and a desire to learn. Whether your background is in software, electronics, data science, AI, or another engineering field, we encourage you to apply. This is an opportunity to gain hands-on experience in SRAM development and contribute to real-world projects spanning memory design, characterization, validation, and compiler implementation.

Internship 1 : Advanced SRAM Design and Self-Timing Optimization

Investigate and optimize SRAM self-timing architectures to improve frequency and robustness for advanced technology nodes, through enhanced bitcell tracking methodologies and adaptive timing path design.

About the Internship

Advanced embedded SRAMs must maintain both robustness and performance across increasingly challenging manufacturing process variations. One key aspect is the design of self-timing mechanisms that accurately track the behaviour of memory bitcells under extreme process conditions. Current solutions combine bitcell tracking and logic-based timing paths, but opportunities exist to improve correlation with worst-case memory behaviour while minimising performance penalties.

What You Will Do

• Analyze the impact of advanced process variations on SRAM self-timing paths.
• Study and benchmark different timing tracking methodologies.
• Investigate bitcell-based and hybrid tracking architectures.
• Develop simulation and evaluation methodologies.
• Propose and validate architectural improvements to improve performance while preserving robustness.

Relevant knowledge and interests

• Microelectronics, CMOS circuit design, and SRAM architecture
• VLSI design, advanced technologies
• Circuit simulation and variability analysis
• Methodical mindset and good presentation skills

Expected outcomes

The internship will provide hands-on exposure to industrial memory IP development and advanced-node design challenges, with the opportunity to contribute to methodologies used in next-generation embedded memory products. We believe this topic would be an excellent opportunity for a curious student seeking experience in advanced integrated circuit design within a leading EDA and IP company.

Internship 2 : Statistical Yield Optimization for Next-Generation SRAM Memories

Develop novel variation-aware methodologies to optimise SRAM robustness and yield under statistical process variations, while minimising the impact on Performance, Power, and Area (PPA).

About the Internship

SRAM memories are a critical component of modern AI and high-performance computing systems. As technology scaling increases device variability, achieving extremely high yield targets requires advanced statistical design methodologies that go beyond conventional margin-based approaches. Optimally balancing robustness across bitcells, sense amplifiers, and peripheral circuits has become a major challenge for next-generation SRAM products.

What You Will Do

• Analyze the impact of statistical process variations on SRAM yield and robustness.
• Investigate yield allocation strategies across SRAM building blocks.
• Develop variation-aware design and optimisation methodologies.
• Evaluate yield versus PPA trade-offs using advanced statistical analysis techniques.
• Propose and validate methodologies to improve overall SRAM rob