Intern, Advanced SRAM & Memory Design

Cadence Design Systems; Valbonne; On-site; EUR 12,000 - 18,000; Full time

Job summary

Cadence Design Systems invites interns to explore advanced SRAM topics at the Sophia-Antipolis campus for a 6-month period starting early 2027. Topics include SRAM self-timing optimization, statistical yield improvements, and power characterization for memory compilers.

You may indicate the topic that best matches your interests and experience. We welcome students from software, electronics, data science, AI, or other engineering fields to apply.

Qualifications

• Foundational knowledge in microelectronics and SRAM design.
• Familiarity with CMOS circuits and VLSI concepts is advantageous.
• Strong problem-solving and communication skills are expected.

Responsibilities

• Analyze SRAM self-timing architectures and their performance under variations.
• Study and benchmark timing-tracking methodologies and architectures.
• Develop simulation and evaluation methodologies for memory IP.
• Propose architectural improvements to boost performance and robustness.
• Contribute to methodologies for memory IP development and compiler design.

Skills

Microelectronics

CMOS circuit design

SRAM architecture

VLSI design

Circuit simulation

Variability analysis

Presentation skills

Education

Student in Electrical Engineering/Computer Engineering

Job description

Cadence Design Systems invites interns to explore advanced SRAM topics at the Sophia-Antipolis campus for a 6-month period starting early 2027. Topics include SRAM self-timing optimization, statistical yield improvements, and power characterization for memory compilers.

You may indicate the topic that best matches your interests and experience. We welcome students from software, electronics, data science, AI, or other engineering fields to apply.