Senior RTL Hardware Design Engineer for AI Compute

Arago; Paris; On-site; EUR 90,000 - 140,000; Full time

Benefits offered by this job

Relocation bonus

Equity

Healthcare coverage

Pension contributions

Professional development

25 days PTO

Public holiday cover

Transport subsidy

Job summary

Arago is searching for a senior RTL/HDL engineer to design and verify custom digital hardware units enabling high-performance AI workloads. You will shape architectures, verify against functional criteria, and ensure tight integration with Arago’s tensor compute platform.

You’ll collaborate with system software and CAD teams, drive verification infrastructure, and contribute to hardware-software co-design across ASIC/FPGA flows. English required; French is a plus.

Qualifications

• Extensive RTL experience with Verilog/SystemVerilog.
• Strong digital-architecture knowledge and integration skills.
• Proficient in functional verification; UVM a plus.
• Experience with ASIC and FPGA design flows.
• Ability to work across the full hardware stack from spec to physical.
• English fluency; French is a plus.

Responsibilities

• Design, implement, and verify RTL blocks for memory, control, and compute subsystems.
• Collaborate with system software and architecture teams to define block-level specs and ensure performance alignment.
• Develop and maintain functional verification infrastructure across simulations and testbenches.
• Support synthesis, timing, and backend integration with CAD engineers.
• Contribute to architectural exploration and hardware-software co-design for future iterations.

Skills

RTL design Verilog

Digital architecture

Functional verification

ASIC/FPGA design

Hardware integration

English proficiency

French a plus

Tools

UVM

Synthesis tools

DFT

FPGA toolchains

Job description

Arago is searching for a senior RTL/HDL engineer to design and verify custom digital hardware units enabling high-performance AI workloads. You will shape architectures, verify against functional criteria, and ensure tight integration with Arago’s tensor compute platform.

You’ll collaborate with system software and CAD teams, drive verification infrastructure, and contribute to hardware-software co-design across ASIC/FPGA flows. English required; French is a plus.