Mixed-Signal IC Design Engineer: RTL to Tape-out + Stock

Arago; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Stock options

Relocation bonus

Healthcare coverage

Pension contributions

25 days PTO

Résumé du poste

Arago in France is seeking a senior digital design engineer to design, integrate, and verify high-performance digital subsystems within mixed-signal ICs, from RTL to tape-out, enabling control, calibration, and high-speed data movement. You will lead the digital implementation flow, collaborate with analog, layout, and system teams to optimize digital-analog boundaries, and integrate external IP blocks such as GPIOs and LVDS.

English proficiency is required; French is a plus.

Qualifications

• Strong experience in digital RTL design for high-speed mixed-signal systems.
• Proven ability to drive digital blocks from design through tape-out in analog/RF ICs.
• Experience integrating external IPs and high-speed SerDes.

Responsabilités

• Design and verify digital subsystems interfacing with high-speed analog and mixed-signal circuits.
• Integrate and customize external IP blocks (GPIOs, LVDS, serial interfaces).
• Lead the digital implementation flow from RTL to tape-out.
• Collaborate with analog, layout, and system teams to co-optimize switches between digital and analog domains.
• Develop high-speed serial I/O subsystems; SerDes experience is a plus.
• English proficiency required; French is a plus.

Connaissances

RTL design

SystemVerilog

Mixed-signal

SerDes

External IP integration

EDA tools

Floorplanning

Tape-out

Timing closure

Outils

GPIOs

LVDS interfaces

SPI/I2C interfaces

Synthesis tools

P&R tools

Description du poste

Arago in France is seeking a senior digital design engineer to design, integrate, and verify high-performance digital subsystems within mixed-signal ICs, from RTL to tape-out, enabling control, calibration, and high-speed data movement. You will lead the digital implementation flow, collaborate with analog, layout, and system teams to optimize digital-analog boundaries, and integrate external IP blocks such as GPIOs and LVDS.

English proficiency is required; French is a plus.