Senior Hardware Design Engineer

Arago Inc.; Paris; Sur place; EUR 70 000 - 120 000; Plein temps

Avantages offerts par ce poste

Competitive cash compensation

Stock option plan

Relocation bonus

Healthcare coverage

Pension contributions

Professional development support

25 days of PTO plus public holidays

Résumé du poste

A cutting-edge technology company located in France is seeking a skilled hardware engineer to design and verify custom digital hardware components. The ideal candidate will have extensive experience in RTL design and a strong understanding of digital architecture. Responsibilities include collaborating with software teams, developing verification infrastructure, and supporting backend integration. This role offers competitive salary, stock options, relocation assistance, and excellent benefits in a dynamic multicultural environment.

Qualifications

• Extensive experience in RTL design for various subsystems.
• Strong understanding of digital architecture and integration.
• Proficiency in functional verification and testbench development.
• Familiarity with ASIC and FPGA design flows.

Responsabilités

• Design and verify custom hardware components and architectures.
• Collaborate to define specifications with software and architecture teams.
• Develop functional verification infrastructure for validation.
• Support synthesis, timing analysis, and backend integration.
• Contribute to future architectural explorations.

Connaissances

RTL design (Verilog/SystemVerilog)

Digital architecture knowledge

Functional verification expertise

ASIC/FPGA design flow familiarity

Full hardware stack proficiency

Description du poste

Meet Arago and the Aragonians

Arago is an AI and computer hardware company whose mission is to drive the course of history forward. We do so by accelerating breakthroughs at the intersection of AI and semiconductors.

Founded in 2024 by AI researchers and physicists with deep expertise in photonics, electronics, software, mathematics, and machine learning, Arago brings together a lean team of engineers and scientists from the world’s top companies and research labs.

Composed of nine nationalities and operating from hubs in France, North America, and Israel, we believe in great science and fast achievements. Our work is guided by these core principles:

1. Do great things: we deliver work we’re proud to sign our name to.

2. High velocity: speed matters. We move quickly, one step at a time.

3. One unit: we’re all in this together, with relationships grounded in trust, respect, and camaraderie.

Arago is backed by executives from Apple, Arm, Nvidia, Microsoft, and Hugging Face, as well as prominent US and European deeptech venture firms and exited founders.

What you’ll do

Design and verify custom digital hardware components and architectures that enable high-performance, tightly integrated computation workloads and interface Arago’s custom tensor unit for advanced AI/ML applications.

Responsibilities

• Design, implement, and verify RTL blocks for memory, control, and compute subsystems within Arago’s custom multiphysics computation unit.

• Collaborate with Arago’s system software and architecture teams to define block-level specifications and ensure alignment with performance and integration goals.

• Develop and maintain functional verification infrastructure to validate design correctness across simulation and hardware testbenches.

• Support synthesis, timing analysis, and backend integration, working closely with Arago’s physical design and CAD engineers.

• Contribute to architectural exploration and hardware-software co-design efforts to shape future iterations of Arago’s compute platform.

Required Skills and Experience

• Extensive experience in RTL design (Verilog/SystemVerilog) for control logic, datapaths, memory subsystems, and specialized processing units.

• Strong understanding of digital architecture, including pipelining, arbitration, memory hierarchy, and system-level integration.

• Proficiency in functional verification, including testbench development, assertions, coverage metrics, and debugging (UVM experience is a plus).

• Familiarity with ASIC and FPGA design flows, including synthesis, timing closure, and DFT.

• Comfortable working across the full hardware stack — from architectural specification and microarchitecture to physical implementation support.

Pay and benefits

• Competitive cash compensation, with final package based on location, experience, and the pay of team members in similar positions.

• Meaningful stock option plan offered at the earliest stage of the company (included in the majority of full time offers).

• Relocation bonus and coverage of moving expenses for relocation within 20 minutes of the company’s location.

• Healthcare coverage (including family-friendly options), pension contributions, professional development support, and 25 days of PTO, in addition to public holidays.

• Ownership of a key technical domain, with significant vertical and/or horizontal growth opportunities, based on performance and individual drive.

• A high-paced, multicultural (with 9 nationalities), and engineering-led environment.