Senior RTL Hardware Design Engineer for AI Compute Platform

Arago; Paris; Sur place; EUR 70 000 - 120 000; Plein temps

Avantages offerts par ce poste

Stock option plan

Relocation bonus

Healthcare coverage

Pension contributions

Professional development support

25 days PTO

Public transport subsidy

Résumé du poste

Arago, an AI and hardware innovator, seeks engineers to design and verify RTL blocks for a high-performance compute platform. You will work across memory subsystems, control logic, and specialized units, collaborating with system software teams to ensure precise integration and timing.

The role emphasizes full-stack hardware expertise, from architecture to physical implementation, plus strong verification and English communication skills.

Qualifications

• Experience in RTL design and verification for control logic, datapaths, and memory subsystems.
• Strong understanding of pipelining, memory hierarchy, and system integration.
• Proficiency with testbench development, assertions, coverage metrics, and debugging (UVM is a plus).
• Familiarity with ASIC/FPGA flows including synthesis, timing closure, DFT.

Responsabilités

• Design, implement, and verify RTL blocks for memory, control, and compute subsystems.
• Collaborate with system software and architecture teams to define block-level specs.
• Develop and maintain functional verification infrastructure across simulation and hardware testbenches.
• Support synthesis, timing analysis, and backend integration with CAD engineers.
• Contribute to architectural exploration and hardware-software co-design efforts.

Connaissances

RTL design

digital architecture

functional verification

ASIC/FPGA flows

hardware stack

English proficiency

Outils

UVM

Description du poste

Arago, an AI and hardware innovator, seeks engineers to design and verify RTL blocks for a high-performance compute platform. You will work across memory subsystems, control logic, and specialized units, collaborating with system software teams to ensure precise integration and timing.

The role emphasizes full-stack hardware expertise, from architecture to physical implementation, plus strong verification and English communication skills.