Senior Mixed-Signal IC Design Engineer

Arago; Paris; Sur place; EUR 90 000 - 150 000; Plein temps

Avantages offerts par ce poste

Stock option plan

Relocation bonus and moving-expense覆盖

Healthcare coverage

Pension contributions

Professional development support

25 days PTO

Résumé du poste

Arago, a France-based AI and hardware company, seeks an experienced digital RTL engineer to design, verify, and tape-out high-performance subsystems for mixed-signal ICs in Paris. You will own RTL to physical implementation and collaborate with analog, layout, and system teams.

Requirements include strong Verilog/SystemVerilog skills for high-speed calibrations, IP integration (GPIOs, LVDS, SPI/I2C), and expertise with EDA toolchains. English proficiency is essential; French is a plus.

Qualifications

• Strong experience in digital RTL design (Verilog/SystemVerilog) for mixed-signal systems.
• Deep understanding of digital-analog integration, timing closure, noise coupling, clock domain crossing, and analog-aware floorplanning.
• Proven ability to drive digital blocks from design through verification, synthesis, floorplanning, P&R, timing, signoff, and tape-out in analog/RF IC contexts.
• Experience integrating and adapting external IPs such as GPIOs, LVDS, SPI/I²C; SerDes experience a plus.
• Proficient with industry-standard EDA toolchains for front-end and back-end, with mixed-signal layout constraints.

Responsabilités

• Design and verify digital subsystems interfacing with high-speed analog/mixed-signal circuits.
• Integrate external IPs (GPIOs, LVDS, serial interfaces) with timing constraints.
• Lead digital implementation flow from RTL to synthesis, floorplanning, P&R, timing, and tape-out.
• Collaborate with analog/layout/system teams to co-optimize digital-analog boundaries.
• Contribute to high-speed SerDes I/O subsystems design and implementation.
• Language: English at a proficient level. French is a plus.

Connaissances

Digital RTL design

Verilog/SystemVerilog

Digital-analog integration

IP integration (GPIOs, LVDS, SPI/I2C)

SerDes experience

Outils

EDA toolchains

Physical design flow

Description du poste

Arago, a France-based AI and hardware company, seeks an experienced digital RTL engineer to design, verify, and tape-out high-performance subsystems for mixed-signal ICs in Paris. You will own RTL to physical implementation and collaborate with analog, layout, and system teams.

Requirements include strong Verilog/SystemVerilog skills for high-speed calibrations, IP integration (GPIOs, LVDS, SPI/I2C), and expertise with EDA toolchains. English proficiency is essential; French is a plus.