Senior Mixed-Signal Verification Engineer for SoC

Arago; Paris; Sur place; EUR 90 000 - 130 000; Plein temps

Avantages offerts par ce poste

Stock options

Healthcare

Pension contributions

Professional development

25 days PTO

Résumé du poste

Arago in Paris is seeking a Senior Mixed-Signal Verification Engineer to own the verification of digital-to-analog interfaces on Arago SoCs, collaborating across analog, RTL, architecture, and firmware teams to ensure sign-off. You will build verification environments, develop tests and coverage, debug RTL and analog interactions, and contribute to a fast-moving, ownership-driven team.

Fluency in English is required, and experience with SystemVerilog, UVM, and scripting will help you succeed in

Qualifications

• Strong hands-on experience in ASIC or SoC verification.
• Experience verifying mixed-signal blocks or digital-to-analog interfaces.
• Strong SystemVerilog skills with UVM or equivalent verification methodology.
• Experience building verification environments, tests, assertions, scoreboards, and functional coverage.
• Good understanding of digital and analog/mixed-signal concepts.
• Fluent English.

Responsabilités

• Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.
• Build and maintain verification environments at block, subsystem, and SoC level.
• Develop tests, assertions, checkers, scoreboards, and functional coverage.
• Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.
• Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
• Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.
• Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.

Connaissances

ASIC/SoC verification

Mixed-signal verification

SystemVerilog / UVM

Debug RTL/analog interfaces

Scripting (Python/Tcl)

English proficiency

Outils

Python

Tcl

Shell

UVM

Description du poste

Arago in Paris is seeking a Senior Mixed-Signal Verification Engineer to own the verification of digital-to-analog interfaces on Arago SoCs, collaborating across analog, RTL, architecture, and firmware teams to ensure sign-off. You will build verification environments, develop tests and coverage, debug RTL and analog interactions, and contribute to a fast-moving, ownership-driven team.

Fluency in English is required, and experience with SystemVerilog, UVM, and scripting will help you succeed in