Senior Mixed-Signal Verification Engineer for SoCs

Arago; Paris; On-site; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Stock options

Healthcare coverage

Pension contributions

25 days PTO

Job summary

Arago in Paris is seeking a Senior Mixed-Signal Verification Engineer to own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago SoCs. You will collaborate with analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.

The role requires strong SystemVerilog skills, practical UVM experience, and the ability to build verification environments, tests, assertions, scoreboards, and

Qualifications

• Strong hands-on experience in ASIC or SoC verification.
• Experience verifying mixed-signal blocks or digital-to-analog and analog-to-digital interfaces.
• Strong SystemVerilog skills and practical experience with UVM or an equivalent verification methodology.
• Experience building verification environments and developing tests, assertions, scoreboards, and functional coverage.
• Good understanding of both digital design fundamentals and basic analog/mixed-signal concepts.
• Strong debugging skills, including the ability to investigate issues spanning RTL, models, clocks, resets, configuration, and analog behavior.
• Experience with scripting and automation, preferably Python, Tcl, shell, or similar.
• Language: English at a proficient level.

Responsibilities

• Own the mixed-signal verification methodology and verification plan for digital-to-analog interfaces on Arago SoCs.
• Build and maintain verification environments at block, subsystem, and SoC level.
• Develop tests, assertions, checkers, scoreboards, and functional coverage.
• Verify digital control and configuration of analog/mixed-signal circuitry across normal operation, corner cases, and error conditions.
• Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
• Develop or integrate behavioral and real-number models needed for efficient mixed-signal simulation.
• Work closely with analog, RTL, architecture, firmware, and SoC verification teams to identify and resolve interface issues.

Skills

ASIC verification

Mixed-signal verification

SystemVerilog

UVM

Verification environments

Digital/analog fundamentals

Debugging RTL/analog

Python scripting

English proficiency

Job description

Arago in Paris is seeking a Senior Mixed-Signal Verification Engineer to own the methodology, planning, and execution of mixed-signal verification for digital-to-analog interfaces on Arago SoCs. You will collaborate with analog, RTL, architecture, and firmware teams to ensure correct integration and drive verification to sign-off.

The role requires strong SystemVerilog skills, practical UVM experience, and the ability to build verification environments, tests, assertions, scoreboards, and