Digital IC Design Engineer – Mixed-Signal RTL to Tape-out

Arago Inc.; Paris; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Stock options

Relocation bonus

Healthcare

PTO 25 days

Transport subsidy

Job summary

Arago Inc. is seeking a senior digital-analog IC design engineer to design, integrate, and deliver high-performance digital subsystems inside mixed-signal ICs, from RTL to tape-out.

You will calibrate, control, and move data at high speeds, interfacing with analog blocks and external IPs. Proficiency in Verilog/SystemVerilog and experience with Virtuoso-like environments are essential, with a focus on timing, power, and layout constraints in RF/analog contexts.

Qualifications

• Strong experience in digital RTL design (Verilog/SystemVerilog) for mixed-signal systems with high-speed calibration/control loops, converters, multiplexers, and data paths.
• Experience with analog IC development environments (Virtuoso or equivalent).
• Deep understanding of digital-analog integration challenges: timing, noise, clock-domain crossing, and analog-aware floorplanning in high-speed environments.
• Proven ability to drive digital blocks end-to-end (design to tape-out) in analog/RF IC contexts.
• Skilled in integrating external IPs (GPIOs, LVDS, SPI/I2C); SerDes experience is a plus.
• Proficient with standard EDA toolchains for front-end and back-end, with mixed-signal layout constraints.

Responsibilities

• Design and verify digital subsystems interfacing with high-speed analog circuits, including calibration engines, control FSMs, data converters, and multiplexing logic.
• Contribute to analog component design at the digital-analog interface: calibration circuits, DACs/ADCs, comparators.
• Integrate and customize external IP blocks (GPIOs, LVDS I/Os, serial interfaces) ensuring timing and signal integrity.
• Lead the digital implementation flow for mixed-signal blocks: RTL to synthesis, floorplanning, P&R, timing closure, tape-out.
• Collaborate with analog, layout, and systems teams to optimize digital-analog boundaries and resolve cross-domain issues.
• Contribute to high-speed SerDes I/O subsystem development; SerDes design is a significant plus.
• Language: English proficient; French is a plus.

Skills

Verilog/SystemVerilog

Mixed-signal design

Calibrations/control loops

Analog-digital integration

SerDes design

Front-end & back-end flow

Clock-domain crossing

Tools

Virtuoso

EDA toolchains

Job description

Arago Inc. is seeking a senior digital-analog IC design engineer to design, integrate, and deliver high-performance digital subsystems inside mixed-signal ICs, from RTL to tape-out.

You will calibrate, control, and move data at high speeds, interfacing with analog blocks and external IPs. Proficiency in Verilog/SystemVerilog and experience with Virtuoso-like environments are essential, with a focus on timing, power, and layout constraints in RF/analog contexts.