Mixed-Signal IC Design Engineer: RTL-to-Tape-Out

Arago; Paris; On-site; EUR 90,000 - 130,000; Full time

Benefits offered by this job

Stock options

Relocation bonus

Healthcare coverage

Pension contributions

Professional development

Public transport subsidy

25 days PTO

Job summary

Arago is an AI and hardware innovator seeking a specialist Digital IC Designer to help build high-performance subsystems in mixed-signal environments, from RTL through tape-out.

You will lead digital implementation, integrate IP blocks, and collaborate with analog, layout, and system teams to ensure robust high-speed performance. English proficiency required; French a plus. Relocation and stock options are offered.

Qualifications

• Strong experience in digital RTL design (Verilog/SystemVerilog) for mixed-signal systems involving high-speed calibration/control loops, converters, multiplexers, and serial/parallel data paths.
• Deep understanding of digital-analog integration challenges, including timing closure, noise coupling, clock domain crossing, and analog-aware floorplanning in high-speed environments.
• Proven ability to drive digital blocks from design through verification, synthesis, floorplanning, P&R, and tape-out, especially in the context of analog or RF ICs.
• Skilled in integrating and adapting external IPs such as GPIOs, LVDS, SPI/I²C interfaces; experience with high-speed serializers/deserializers (SerDes) is a highly valued plus.
• Proficient with industry-standard EDA toolchains for both front-end (design/verification) and back-end (physical implementation), with a strong grasp of mixed-signal layout constraints.

Responsibilities

• Design and verify digital subsystems that interface directly with high-speed analog and mixed-signal circuits — including calibration engines, control FSMs, data converters, and multiplexing logic.
• Integrate and customize external IP blocks (e.g., GPIOs, LVDS I/Os, serial interfaces), ensuring compliance with analog signal and timing requirements.
• Lead the digital implementation flow for mixed-signal blocks: from RTL to synthesis, floorplanning, P&R, timing closure, physical signoff, and tape-out.
• Collaborate closely with analog, layout, and system teams to co-optimize digital-analog boundaries, resolve cross-domain issues, and ensure robust high-speed performance.
• Contribute to the development of high-speed serial I/O subsystems — experience in the design and implementation of SerDes blocks is a significant advantage.
• Language: English at a proficient level. French is a plus.

Skills

Digital RTL design

Verilog/SystemVerilog

Digital-analog integration

Timing closure

RTL to tape-out

SerDes design

Tools

EDA toolchains

Job description

Arago is an AI and hardware innovator seeking a specialist Digital IC Designer to help build high-performance subsystems in mixed-signal environments, from RTL through tape-out.

You will lead digital implementation, integrate IP blocks, and collaborate with analog, layout, and system teams to ensure robust high-speed performance. English proficiency required; French a plus. Relocation and stock options are offered.