Principal Design Verification Engineer - SoC Systems

Arteris; Biot; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

Arteris is seeking a Senior Staff / Principal Design Verification Engineer to join our team in Biot, France. You will help design interconnect and memory hierarchy solutions for leading SoCs, blending RTL with software to create configurable, testable verification flows.

You will influence architecture, verification, and tooling within an experienced group. Key responsibilities include UVM-based test bench development, system-level verification, RTL debugging in Verilog/SystemVerilog, and

Qualifications

• Strong RTL (Verilog) and UVM/C test bench debugging skills.
• Experience integrating vendor-provided VIPs for unit and system-level verification.
• Familiar with Arm AMBA protocols and system-level verification.
• Exposure to automation tooling and regression workflows.

Responsabilités

• UVM based test bench development and debugging.
• Define, document, develop, and execute RTL verification test/coverage at the system level.
• Triaging regressions and debugging RTL designs in Verilog and SystemVerilog.
• Improve verification processes, methodologies, and metrics.
• Develop and maintain automation tools to improve frontend design and verification.
• Monitor systems, diagnose issues, and run regressions/ Jenkins.

Connaissances

RTL Verilog

UVM test bench

Scripting: Python/JavaScript

Debugging

Formation

MS in EE/CS or equivalent

BS in EE/CS

Outils

Jenkins CI

Arm AMBA protocols

Description du poste

Arteris is seeking a Senior Staff / Principal Design Verification Engineer to join our team in Biot, France. You will help design interconnect and memory hierarchy solutions for leading SoCs, blending RTL with software to create configurable, testable verification flows.

You will influence architecture, verification, and tooling within an experienced group. Key responsibilities include UVM-based test bench development, system-level verification, RTL debugging in Verilog/SystemVerilog, and