Mixed-Signal IC Design Engineer: RTL to Tape-Out

Arago Inc.; Paris; Sur place; EUR 110 000 - 140 000; Plein temps

Avantages offerts par ce poste

Stock options

Relocation assistance

Healthcare coverage

Pension contributions

Professional development support

25 days PTO

Public holidays

Résumé du poste

Arago is seeking a senior digital RTL designer to design, verify, and deliver high-performance digital subsystems inside mixed-signal ICs. You will own the flow from RTL to physical implementation and tape-out, interfacing with analog teams to optimize cross-domain performance.

The role emphasizes Verilog/SystemVerilog expertise, hands-on EDA toolchain use, and collaboration across hardware disciplines. English is required; French is a plus, and relocation support is provided.

Qualifications

• Strong experience in digital RTL design for mixed-signal systems.
• Deep understanding of digital-analog integration, timing closure, and noise coupling.
• Proven ability to drive digital blocks from design through verification, synthesis, floorplanning, P&R, and tape-out.
• Experience integrating external IPs such as GPIOs, LVDS, SPI/I2C interfaces; SerDes experience is valued.
• Proficiency with industry-standard EDA toolchains for front-end and back-end, and mixed-signal layout constraints.

Responsabilités

• Design and verify digital subsystems interfacing with high-speed analog/mixed-signal circuits.
• Integrate external IP blocks, ensuring timing and signal integrity.
• Lead the digital implementation flow from RTL to tape-out.
• Collaborate with analog/layout/system teams to optimize cross-domain performance.
• Develop high-speed serial I/O subsystems; SerDes experience is a plus.

Connaissances

Verilog/SystemVerilog

RTL design

Mixed-signal systems

Timing closure

Clock domain crossing

Analog floorplanning

SerDes

IP integration

EDA toolchains

Design verification

Outils

GPIOs/LVDS

SPI/I2C interfaces

Synthesis tools

Floorplanning tools

Verificatio­n tools

Description du poste

Arago is seeking a senior digital RTL designer to design, verify, and deliver high-performance digital subsystems inside mixed-signal ICs. You will own the flow from RTL to physical implementation and tape-out, interfacing with analog teams to optimize cross-domain performance.

The role emphasizes Verilog/SystemVerilog expertise, hands-on EDA toolchain use, and collaboration across hardware disciplines. English is required; French is a plus, and relocation support is provided.