Senior Mixed-Signal Verification Engineer — SoC/ASIC

Arago Inc.; Paris; Sur place; EUR 85 000 - 120 000; Plein temps

Avantages offerts par ce poste

Competitive cash compensation

Stock options

Healthcare coverage

Pension contributions

Professional development support

25 days PTO + holidays

Résumé du poste

Arago Inc. seeks a Senior Mixed-Signal Verification Engineer to own planning and execution for mixed-signal verification on Arago SoCs. You will work across analog, RTL, architecture, and firmware teams to ensure correct integration and sign-off of digital-to-analog interfaces.

You will build verification environments, develop tests and coverage, and debug issues spanning RTL, clocks, and analog behavior while advancing the verification methodology within a fast-paced, collaborative environment.

Qualifications

• Experience verifying ASIC or SoC designs.
• Strong background in mixed-signal blocks including D/A and A/D interfaces.
• Proficient SystemVerilog with UVM or equivalent verification methodology.
• Experience building verification environments, tests, assertions, scoreboards and coverage.
• Solid understanding of digital design and analog/mixed-signal concepts.
• Strong debugging across RTL, models, clocks, resets, configuration and analog behavior.
• Scripting and automation experience (Python, Tcl, shell or similar).
• English language proficiency required.

Responsabilités

• Own the mixed-signal verification methodology and verification plan for D/A interfaces on Arago SoCs.
• Build and maintain verification environments at block, subsystem, and SoC levels.
• Develop tests, assertions, checkers, scoreboards and functional coverage.
• Verify digital control and configuration of analog/mixed-signal circuitry across normal operation and corner cases.
• Run regressions, analyze coverage, debug failures, and drive verification to sign-off.
• Develop or integrate behavioral and real-number models for efficient mixed-signal simulation.
• Collaborate with analog, RTL, architecture, firmware and SoC verification teams to resolve interfaces.

Connaissances

ASIC/SoC verification

Mixed-signal verification

SystemVerilog/UVM

Verification environments

Digital/Analog concepts

RTL/firmware debugging

Scripting (Python/Tcl/Shell)

English proficiency

Description du poste

Arago Inc. seeks a Senior Mixed-Signal Verification Engineer to own planning and execution for mixed-signal verification on Arago SoCs. You will work across analog, RTL, architecture, and firmware teams to ensure correct integration and sign-off of digital-to-analog interfaces.

You will build verification environments, develop tests and coverage, and debug issues spanning RTL, clocks, and analog behavior while advancing the verification methodology within a fast-paced, collaborative environment.