Senior RTL Verification Engineer - Hybrid SoC Focus

Arm; Valbonne; Hybride; EUR 61 000 - 82 000; Plein temps

Résumé du poste

Arm in Valbonne, France, is seeking a Senior Verification Engineer to verify RTL implementing upcoming features in ARM SoCs, ensuring new functionality and existing features meet architectural requirements.

You will collaborate with the RTL team, develop and enhance verification environments, write verification plans, and mentor junior engineers. A background in SystemVerilog, UVM, ARM architectures, and scripting is essential.

Qualifications

• Minimum of 3 years of proven IP/SOC verification experience.
• Advanced proficiency in SystemVerilog and Verilog with deep UVM knowledge.
• Solid understanding of SoC verification using C testcases.
• Experience writing verification plans and test plans.
• Experience with Testbench development using standard methodologies.
• Experience with ARM-based designs and/or ARM architectures.
• Experience with Perl, Python, or other scripting languages.
• Strong interpersonal skills to collaborate with multi-functional teams.

Responsabilités

• Collaborate closely with the RTL team to understand microarchitecture details.
• Develop new verification environments and enhance existing ones, including stimulus generators and checkers.
• Verify new features function as specified and do not impact existing functionality.
• Implement verification strategies in partnership with other verification engineers.
• Contribute to continuous improvement in verification methodology based on learnings.
• Mentor early-tenure verification engineers.

Connaissances

SystemVerilog

Verilog

UVM

C Testcases

Testbench development

ARM architectures

Perl

Python

Team collaboration

Formation

Bachelor's or Master's in CS/EE

Outils

AMBA protocols

Description du poste

Arm in Valbonne, France, is seeking a Senior Verification Engineer to verify RTL implementing upcoming features in ARM SoCs, ensuring new functionality and existing features meet architectural requirements.

You will collaborate with the RTL team, develop and enhance verification environments, write verification plans, and mentor junior engineers. A background in SystemVerilog, UVM, ARM architectures, and scripting is essential.