Senior Digital Verification Architect – ASIC/SoC

NXP Semiconductors NV; Grenoble; On-site; EUR 90,000 - 130,000; Full time

Job summary

NXP Semiconductors Netherlands B.V. seeks a Senior HW Digital Design Verification Engineer to define and implement verification strategies for complex digital ASIC/SoC blocks. The role emphasizes robust testbenches, coverage, and cross-functional collaboration.

You will work with SystemVerilog, UVM, and formal methods, creating advanced verification environments and mentoring junior engineers in a dynamic team.

Qualifications

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 5+ years of experience in digital design verification of complex ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM.
• Experience with test plans and verification environments from scratch.

Responsibilities

• Develop verification plans for complex digital blocks and sub-systems.
• Implement UVM and formal verification techniques.
• Create and maintain verification environments with SystemVerilog, UVM, and e.
• Develop directed, constrained-random, and assertion-based testbenches.
• Perform functional and code coverage analysis.
• Debug design and verification issues with engineers to find root causes.
• Collaborate with design, architecture, and software teams.
• Mentor junior engineers and share expertise.

Skills

SystemVerilog

UVM

Test plans

Constrained-random

Python

Debugging

Teamwork

Education

Bachelor’s or Master’s degree

Tools

Simulators

Waveform viewers

Coverage tools

Tcl

Job description

NXP Semiconductors Netherlands B.V. seeks a Senior HW Digital Design Verification Engineer to define and implement verification strategies for complex digital ASIC/SoC blocks. The role emphasizes robust testbenches, coverage, and cross-functional collaboration.

You will work with SystemVerilog, UVM, and formal methods, creating advanced verification environments and mentoring junior engineers in a dynamic team.