Senior HW Digital Design Verification Engineer

NXP Semiconductors NV; Grenoble; Vor Ort; EUR 90.000 - 130.000; Vollzeit

Zusammenfassung

NXP Semiconductors Netherlands B.V. seeks a Senior HW Digital Design Verification Engineer to define and implement verification strategies for complex digital ASIC/SoC blocks. The role emphasizes robust testbenches, coverage, and cross-functional collaboration.

You will work with SystemVerilog, UVM, and formal methods, creating advanced verification environments and mentoring junior engineers in a dynamic team.

Qualifikationen

• Bachelor’s or Master’s degree in Electrical or Computer Engineering.
• 5+ years of experience in digital design verification of complex ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM.
• Experience with test plans and verification environments from scratch.

Aufgaben

• Develop verification plans for complex digital blocks and sub-systems.
• Implement UVM and formal verification techniques.
• Create and maintain verification environments with SystemVerilog, UVM, and e.
• Develop directed, constrained-random, and assertion-based testbenches.
• Perform functional and code coverage analysis.
• Debug design and verification issues with engineers to find root causes.
• Collaborate with design, architecture, and software teams.
• Mentor junior engineers and share expertise.

Kenntnisse

SystemVerilog

UVM

Test plans

Constrained-random

Python

Debugging

Teamwork

Ausbildung

Bachelor’s or Master’s degree

Tools

Simulators

Waveform viewers

Coverage tools

Tcl

Jobbeschreibung

Job Summary

NXP Semiconductors Netherlands B.V. is seeking a highly skilled and experienced Senior HW Digital Design Verification Engineer to join our dynamic team. In this role, you will be responsible for defining and implementing comprehensive verification strategies for complex digital designs, ensuring the robustness and correctness of our cutting-edge semiconductor products.

Job Responsibilities

• Develop and execute detailed verification plans for complex digital blocks and sub-systems, including testbench architecture, testcase development, and coverage closure.
• Implement advanced verification methodologies such as UVM (Universal Verification Methodology) and formal verification techniques.
• Create and maintain verification environments using industry-standard tools and languages (e.g., SystemVerilog, UVM, OVM, e).
• Develop directed, constrained-random, and assertion-based testbenches to thoroughly validate design functionality and performance.
• Perform functional and code coverage analysis to ensure verification completeness.
• Debug complex design and verification issues, working closely with design engineers to identify root causes and propose solutions.
• Collaborate with design, architecture, and software teams to understand design specifications and requirements.
• Contribute to continuous improvement of verification methodologies, flows, and tools.
• Mentor junior engineers and share technical expertise within the team.

Job Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 5+ years of experience in digital design verification of complex ASICs/SoCs.
• Strong proficiency in SystemVerilog and UVM.
• Demonstrated experience in developing comprehensive test plans and verification environments from scratch.
• Solid understanding of digital design principles, computer architecture, and communication protocols.
• Experience with industry-standard EDA verification tools (e.g., simulators, waveform viewers, coverage analysis tools).
• Familiarity with scripting languages (e.g., Python, Perl, Tcl).
• Experience with formal verification techniques is a plus.
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and interpersonal skills, with the ability to work effectively in a collaborative team environment.

More information about NXP in France…

#LI-7795