Senior AMS Verification Engineer – Analog/Mixed-Signal

NXP Semiconductors NV; Caen; On-site; EUR 90,000 - 130,000; Full time

Job summary

NXP Semiconductors Netherlands B.V. is seeking a talented AMS Verification Engineer to join our team. You will verify complex analog/mixed-signal ICs, ensuring they meet performance and reliability specs.

You will develop verification plans, environments, testbenches, and ABV within SystemVerilog/UVM, run mixed-signal simulations, analyze results, and collaborate with design engineers to improve verifiability. You will also drive regression testing and document coverage and sign-off reports.

Qualifications

• Master’s degree or Ph.D. in Electrical Engineering, Computer Engineering, or a related field.
• 8+ years of AMS verification experience on complex ICs.
• Strong understanding of analog circuit design fundamentals (e.g., op-amps, ADCs, DACs, PLLs).
• Proficiency in SystemVerilog and UVM for mixed-signal verification.
• Hands-on experience with mixed-signal simulation tools (Cadence Virtuoso, Spectre, Xcelium, QuestaSim).
• Experience with scripting languages (Python, Perl, Tcl) for test automation and data analysis.

Responsibilities

• Develop and execute verification plans for AMS blocks and systems.
• Create verification environments using SystemVerilog, UVM, and other methodologies.
• Develop testbenches, test cases, and ABV for AMS designs.
• Perform mixed-signal simulations and analyze results to identify issues.
• Collaborate with design engineers to improve verifiability.
• Develop and automate regression testing procedures for coverage.

Skills

Problem solving

Communication

Attention to detail

Team collaboration

Education

Master’s degree or Ph.D. in Electrical Engineering / Computer Engineering or related field

Tools

SystemVerilog

UVM

Cadence Virtuoso

Spectre

Xcelium

QuestaSim

Python

Perl

Tcl

Job description

NXP Semiconductors Netherlands B.V. is seeking a talented AMS Verification Engineer to join our team. You will verify complex analog/mixed-signal ICs, ensuring they meet performance and reliability specs.

You will develop verification plans, environments, testbenches, and ABV within SystemVerilog/UVM, run mixed-signal simulations, analyze results, and collaborate with design engineers to improve verifiability. You will also drive regression testing and document coverage and sign-off reports.