Senior Verification Engineer, SoC/RTL (Hybrid)

Arm; Valbonne; Hybride; EUR 60 500 - 81 900; Plein temps

Résumé du poste

Arm in Sophia Antipolis, France, seeks a Senior Verification Engineer to verify RTL implementing upcoming ARM SoC features, ensuring both new functionality and existing features meet architectural requirements.

You will collaborate with the RTL team, develop and optimize verification environments, and mentor junior engineers while driving verification plans and testbenches across the project.

Qualifications

• 3+ years of proven IP/SOC verification experience
• Advanced proficiency in SystemVerilog and Verilog with deep knowledge of UVM Methodology
• Solid understanding of SoC verification using C testcases
• Experience writing verification plans and test plans
• Experience with Testbench development using standard verification methodologies
• Experience with ARM-based designs and/or ARM System Architectures
• Experience with Perl, Python, or other scripting languages
• Strong interpersonal skills to collaborate with multi-functional and geographically distributed teams

Responsabilités

• Collaborate with the RTL team to understand microarchitecture details
• Develop and enhance verification environments, stimuli generators, and checkers
• Verify new features meet specifications and do not impact existing functionality
• Implement verification strategies in partnership with other verification engineers
• Contribute to continuous improvement in verification methodology
• Mentor early-tenure verification engineers

Connaissances

SystemVerilog

Verilog

UVM

RTL verification

C Testcases

Verification plan

Testbench development

ARM-based designs

Python

Scripting languages

Description du poste

Arm in Sophia Antipolis, France, seeks a Senior Verification Engineer to verify RTL implementing upcoming ARM SoC features, ensuring both new functionality and existing features meet architectural requirements.

You will collaborate with the RTL team, develop and optimize verification environments, and mentor junior engineers while driving verification plans and testbenches across the project.