Principal Design Verification Engineer

Arteris; Biot; Sur place; EUR 90 000 - 120 000; Plein temps

Résumé du poste

Arteris is seeking a Senior Staff / Principal Design Verification Engineer to join our team in Biot, France. You will help design interconnect and memory hierarchy solutions for leading SoCs, blending RTL with software to create configurable, testable verification flows.

You will influence architecture, verification, and tooling within an experienced group. Key responsibilities include UVM-based test bench development, system-level verification, RTL debugging in Verilog/SystemVerilog, and

Qualifications

• Strong RTL (Verilog) and UVM/C test bench debugging skills.
• Experience integrating vendor-provided VIPs for unit and system-level verification.
• Familiar with Arm AMBA protocols and system-level verification.
• Exposure to automation tooling and regression workflows.

Responsabilités

• UVM based test bench development and debugging.
• Define, document, develop, and execute RTL verification test/coverage at the system level.
• Triaging regressions and debugging RTL designs in Verilog and SystemVerilog.
• Improve verification processes, methodologies, and metrics.
• Develop and maintain automation tools to improve frontend design and verification.
• Monitor systems, diagnose issues, and run regressions/ Jenkins.

Connaissances

RTL Verilog

UVM test bench

Scripting: Python/JavaScript

Debugging

Formation

MS in EE/CS or equivalent

BS in EE/CS

Outils

Jenkins CI

Arm AMBA protocols

Description du poste

Do you want to contribute to the backbone of some of the world’s most popular SoCs? As a Senior Staff / Principal Design Verification Engineer at Arteris, you will work with an expert team to design and deliver interconnect & memory hierarchy solutions for some of the world’s most sophisticated mobile, telecom, automotive, and consumer SoC designs. You will create designs in a powerful language that blends traditional RTL with leading-edge software to provide extremely configurable, testable, and high-quality solutions. You will go home at the end of the day, amazed at all the places where your creations end up. You will have the opportunity to be part of a proven, successful startup, and to influence the development environment, architecture, verification, and everything in-between – you will no longer be stuck in a silo or just a cog in the machine. Your co-workers will be an experienced team of industry experts who love what they do.

Key Responsibilities

• UVM based test bench development and debugging
• Defining, documenting, developing, and executing RTL verification test/coverage at the system level
• Triaging Regressions, Debugging RTL designs in Verilog and System Verilog
• Help improve and refine the verification process, methodology, and metrics
• Develop, maintain, and test engineering design automation tools infrastructure to improve our frontend design and verification process.
• Monitor automated systems, isolate problems, and perform routine diagnostics checks & repairs.
• Run regressions, configure Jenkins builds, and record regression data
• Build/maintain regression dashboards & database to view trends and progress in numerical and graphical formats
• Evaluate existing automation infrastructure for areas of improvement
• Provide clear, concise documentation of the implementation/flow and usage of automation processes.

Experience Requirements / Qualifications

• Verification flow enhancements using a scripting language such as Shell scripts, Python & JavaScript
• Strong RTL (Verilog) and UVM/C test bench debugging skills
• Experience integrating vendor-provided VIPs for unit and system-level verification
• Experience with Arm AMBA protocols
• This opportunity involves high-performance, low-power designs on a highly visible project

Education Requirements

• MS degree in EE, CS, or equivalent preferred. BS degree minimum.