Senior Digital IC Backend Engineer — Stock Options

Arago; Paris; Sur place; EUR 80 000 - 120 000; Plein temps

Avantages offerts par ce poste

Competitive cash compensation

Stock option plan

Relocation bonus

Healthcare coverage

Pension contributions

Professional development support

25 days PTO

Public holidays

Transport subsidy

Résumé du poste

Arago is seeking a Digital Backend Design Engineer to implement physical designs from RTL to GDSII. You will work with RTL, DFT, and packaging teams to optimize PPA, timing, and yield while meeting tapeout deadlines.

You should have a PhD or master in EE, 4+ years in backend IC design, and strong Tcl scripting skills. English is required; French is a plus. This role offers relocation support and a fast-paced, engineering-led environment.

Qualifications

• Master’s or PhD in Electrical/Electronic Engineering or related field.
• 4+ years experience in digital IC backend implementation.
• Proficiency with backend EDA tools, Cadence Innovus and Genus.
• Strong understanding of P&R, STA, DRC/LVS, IR drop and EM analysis.
• Experience with technology nodes 22nm or below.
• Skilled in Tcl scripting for backend flows.
• Experience in hierarchical or full-chip implementation is preferred.
• English at proficient level; French is a plus.

Responsabilités

• Execute full-chip and block-level physical design tasks including floorplanning, placement, clock tree synthesis, routing, and physical verification.
• Develop and optimize the digital backend flow.
• Drive timing closure, power optimization, and physical verification (LVS/DRC/ERC).
• Collaborate with front-end designers to address timing and interface issues.
• Support tapeout preparation and final sign-off processes.

Connaissances

Digital backend implementation

Place & route (P&R)

Static timing analysis (STA)

DRC/LVS verification

IR drop analysis

Electromigration (EM) analysis

Technology nodes 22nm or below

Tcl scripting

Hierarchical/full-chip implementation

English proficiency

Formation

Master’s or PhD in Electrical/Electronic Engineering

Outils

Cadence Innovus

Genus

Description du poste

Arago is seeking a Digital Backend Design Engineer to implement physical designs from RTL to GDSII. You will work with RTL, DFT, and packaging teams to optimize PPA, timing, and yield while meeting tapeout deadlines.

You should have a PhD or master in EE, 4+ years in backend IC design, and strong Tcl scripting skills. English is required; French is a plus. This role offers relocation support and a fast-paced, engineering-led environment.