Lead Debug/Trace/Profiling Design Engineer

SiFive, Inc.; La Ciotat; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

SiFive, Inc. is seeking a skilled engineer in La Ciotat to architect, design, and implement debug and profiling hardware. You will collaborate with various teams to optimize hardware performance and configuration.

The ideal candidate has over 7 years of experience in RTL design, strong knowledge of CPU architectures, and excellent teamwork skills. This role may require verification for export-controlled technology access.

Qualifications

• 7+ years of industry experience in architecture and RTL design for debug/trace/profiling hardware.
• Knowledgeable in JTAG and cJTAG interfaces.
• Experience using debugging tools and profiling methods.

Responsabilités

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture and performance teams on exploration and specification.
• Implement RTL generators for configurability as a first-class consideration.

Connaissances

Debug, trace and profiling architecture concepts

CPU architectures

Hardware (RTL) design in Verilog, System Verilog or VHDL

Attention to detail

Teamwork

Object-oriented or functional programming

Chisel/Scala, RISC-V architecture

Formation

MS/PhD in EE, CE, CS or related technical discipline

Outils

Git

Jira

Confluence

Description du poste

Job Responsibilities

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators such that elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with the design verification team to create and execute thorough verification test plans.
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.

Position Requirements

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience in debugging tools, profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of one or more of: Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
• MS/PhD in EE, CE, CS or a related technical discipline.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of right to work in France. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer.