Senior Debug, Trace & Profiling Architect for SoCs

SiFive, Inc.; La Ciotat; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

SiFive, Inc. is seeking a skilled engineer in La Ciotat to architect, design, and implement debug and profiling hardware. You will collaborate with various teams to optimize hardware performance and configuration.

The ideal candidate has over 7 years of experience in RTL design, strong knowledge of CPU architectures, and excellent teamwork skills. This role may require verification for export-controlled technology access.

Qualifications

• 7+ years of industry experience in architecture and RTL design for debug/trace/profiling hardware.
• Knowledgeable in JTAG and cJTAG interfaces.
• Experience using debugging tools and profiling methods.

Responsabilités

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture and performance teams on exploration and specification.
• Implement RTL generators for configurability as a first-class consideration.

Connaissances

Debug, trace and profiling architecture concepts

CPU architectures

Hardware (RTL) design in Verilog, System Verilog or VHDL

Attention to detail

Teamwork

Object-oriented or functional programming

Chisel/Scala, RISC-V architecture

Formation

MS/PhD in EE, CE, CS or related technical discipline

Outils

Git

Jira

Confluence

Description du poste

SiFive, Inc. is seeking a skilled engineer in La Ciotat to architect, design, and implement debug and profiling hardware. You will collaborate with various teams to optimize hardware performance and configuration.

The ideal candidate has over 7 years of experience in RTL design, strong knowledge of CPU architectures, and excellent teamwork skills. This role may require verification for export-controlled technology access.