Senior Debug, Trace & Profiling Hardware Engineer

SiFive, Inc.; La Ciotat; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

SiFive, Inc. is seeking a hardware design engineer in La Ciotat, France, to develop leading debug, trace and profiling IP for RISC-V architecture. In this role, you'll work with cross-functional teams, creating hardware designs that support the rapid development of customizable processor cores.

The ideal candidate will have over 7 years of industry experience, an MS/PhD in a related field, and proficiency in Verilog or System Verilog. This position offers competitive compensation and the opportunity to be part of a pioneering company in processor design.

Qualifications

• 7+ years of industry experience in architecture and RTL design for debug/trace/profiling hardware.
• Attention to detail and focus on high-quality design.
• Ability to work collaboratively in a team.

Responsabilités

• Architect, design and implement debug, trace and profiling hardware.
• Collaborate with architecture and performance teams.
• Integrate new design content into the Chisel/FIRRTL framework.

Connaissances

Knowledgeable in debug, trace and profiling architecture

Experience in debugging tools and profiling methods

Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL

Knowledge of Chisel/Scala, RISC-V architecture

Formation

MS/PhD in EE, CE, CS or a related technical discipline

Outils

Git

Jira

Confluence

Description du poste

SiFive, Inc. is seeking a hardware design engineer in La Ciotat, France, to develop leading debug, trace and profiling IP for RISC-V architecture. In this role, you'll work with cross-functional teams, creating hardware designs that support the rapid development of customizable processor cores.

The ideal candidate will have over 7 years of industry experience, an MS/PhD in a related field, and proficiency in Verilog or System Verilog. This position offers competitive compensation and the opportunity to be part of a pioneering company in processor design.