Debug/Trace/Profiling Design Engineer

SiFive France SASU; La Ciotat; On-site; EUR 70,000 - 90,000; Full time

Job summary

SiFive France SASU is seeking a passionate hardware design engineer to create industry-leading debug, trace, and profiling IP essential for the adoption of RISC-V architecture in SoC designs.

Responsibilities include designing debug hardware, collaborating with various teams, and ensuring documentation for a collaborative culture. Ideal candidates should possess 7+ years of industry experience and a relevant degree.

Qualifications

• 7+ years of industry experience in architecture and RTL design for debug/trace/profiling hardware.
• Proficient in high-quality design practices and teamwork.

Responsibilities

• Design and implement debug, trace and profiling hardware.
• Collaborate with architecture, performance, software, and hardware teams.
• Ensure documentation and a culture of collaborative design.

Skills

Debug, trace and profiling architecture

Debug interfaces, JTAG, cJTAG

CPU architectures

Debugging tools, profiling methods

RTL design in Verilog, System Verilog, or VHDL

Object-oriented and/or functional programming

Chisel/Scala, RISC-V architecture

Git/Jira/Confluence

Education

MS/PhD in EE, CE, CS or a related technical discipline

Job description

Job Description

SiFive is seeking a hardware design engineer who is passionate about designing industry‑leading debug, trace and profiling IP to help drive the tidal wave of adoption of RISC‑V as the architecture of choice for SOC designs across a broad variety of vertical applications.

Responsibilities

• Architect, design and implement debug, trace and profiling hardware.
• Work with architecture, performance, software and hardware teams in architecture/microarchitecture exploration and specification.
• Implement RTL generators such that elements self‑configure to optimally design‑in extensive configurability as a first‑class consideration.
• Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework to enable automatic configuration/generation of documentation, verification testbenches and tests, and packaged software.
• Perform initial sandbox verification, and work with design verification team to create and execute thorough verification test plans.
• Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.

Requirements

• Knowledgeable in debug, trace and profiling architecture and concepts.
• Knowledgeable in debug interfaces, JTAG, cJTAG.
• Knowledgeable in CPU architectures, power management and SoC design.
• Experience in debugging tools, profiling methods.
• Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
• Attention to detail and a focus on high‑quality design.
• Ability to work well with others and a belief that engineering is a team sport.
• Knowledge of at least one object‑oriented and/or functional programming language.
• Knowledge of one or more: Chisel/Scala, RISC‑V architecture, Git/Jira/Confluence is a plus.
• 7+ years of industry experience leading and directly contributing to architecture, microarchitecture and RTL design for debug/trace/profiling hardware for high‑performance processors.
• MS/PhD in EE, CE, CS or a related technical discipline.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in France. Any offer of employment for this position is also contingent on the Company verifying that you are authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.