Senior Debug, Trace & Profiling RTL Engineer

SiFive France SASU; La Ciotat; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

SiFive France SASU is seeking a passionate hardware design engineer to create industry-leading debug, trace, and profiling IP essential for the adoption of RISC-V architecture in SoC designs.

Responsibilities include designing debug hardware, collaborating with various teams, and ensuring documentation for a collaborative culture. Ideal candidates should possess 7+ years of industry experience and a relevant degree.

Qualifications

• 7+ years of industry experience in architecture and RTL design for debug/trace/profiling hardware.
• Proficient in high-quality design practices and teamwork.

Responsabilités

• Design and implement debug, trace and profiling hardware.
• Collaborate with architecture, performance, software, and hardware teams.
• Ensure documentation and a culture of collaborative design.

Connaissances

Debug, trace and profiling architecture

Debug interfaces, JTAG, cJTAG

CPU architectures

Debugging tools, profiling methods

RTL design in Verilog, System Verilog, or VHDL

Object-oriented and/or functional programming

Chisel/Scala, RISC-V architecture

Git/Jira/Confluence

Formation

MS/PhD in EE, CE, CS or a related technical discipline

Description du poste

SiFive France SASU is seeking a passionate hardware design engineer to create industry-leading debug, trace, and profiling IP essential for the adoption of RISC-V architecture in SoC designs.

Responsibilities include designing debug hardware, collaborating with various teams, and ensuring documentation for a collaborative culture. Ideal candidates should possess 7+ years of industry experience and a relevant degree.