Sr. Staff Hardware Design Engineer

SiFive; La Ciotat; Sur place; EUR 70 000 - 90 000; Plein temps

Résumé du poste

A leading compute technology firm is seeking a Senior Hardware Design Engineer to lead the development of a specialized MSI Translation Engine. This role requires expertise in RTL design, memory systems, and virtualization mechanisms. Responsibilities include designing and optimizing memory hierarchies while collaborating with cross-functional teams. A successful candidate will have 7+ years experience and a relevant MS/PhD degree, and must demonstrate proficiency in Chisel and SystemVerilog.

Qualifications

• 7+ years of industry experience in RTL design.
• Deep knowledge of memory systems like TLB design and cache controllers.
• Strong understanding of IOMMU mechanisms and hypervisor-level memory isolation.

Responsabilités

• Own the microarchitecture of the MSI Translation Engine.
• Develop RTL generators using Chisel, focusing on modularity.
• Design and optimize internal memory hierarchies.

Connaissances

RTL design

Memory management

Interrupt controllers

Complex SoC IP

Virtualization expertise

Object-oriented programming

Functional programming

Formation

MS/PhD in EE, CE, or related technical discipline

Outils

Chisel

Scala

SystemVerilog

Verilog

Description du poste

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications. SiFive’s compute platforms enable leading technology companies to innovate, optimize and deliver advanced solutions across AI, machine learning, automotive, data center, mobile, and consumer markets. SiFive is committed to connecting with talented individuals who are passionate about driving innovation.

Job Description

Role: Senior Hardware Design Engineer — IOMMU and Virtualization architectures. SiFive is expanding its virtualization capabilities with a specialized MSI Translation Engine (MTE) that leverages IOMMU-like mechanisms for Message Signaled Interrupt (MSI) translation. You will lead the development of the MTE, ensuring secure translation and delivery of interrupts to the correct Guest OS or Hypervisor context. The role sits at the intersection of core MMU design and system-level interconnects. You will work with our Chisel-based hardware generation framework to build highly configurable IP that scales from embedded systems to complex server-class SoCs.

Responsibilities

• Micro Architecture & Design: Own the microarchitecture of the MSI Translation Engine, meeting strict latency and throughput targets for HPC and automotive applications.
• RTL Implementation: Develop RTL generators using Chisel (Scala), focusing on modularity and extreme configurability.
• Memory System Optimization: Design and optimize the MTE’s internal memory hierarchy, including TLBs, MSHRs, and local metadata caches.
• Cross-Functional Collaboration: Align MTE behavior with the RISC-V AIA (Advanced Interrupt Architecture) and H-extension specifications with Core MMU and Architecture teams.
• Verification & Physical Design: Create rigorous test plans with DV teams for complex corners (e.g., page faults during interrupt translation) and ensure timing closure on advanced process nodes with Physical Design.

Position Requirements

• 7+ years of industry experience in RTL design, focusing on memory management, interrupt controllers, or complex SoC IP.
• Deep knowledge of memory systems: TLB design, MSHRs, cache controllers.
• Virtualization expertise: Strong understanding of IOMMU mechanisms, two-stage address translation, and hypervisor-level memory isolation.
• Experience with RISC-V LTI (Look-aside Translation Interface) offloading address translation from I/O devices to the IOMMU/MTE is a plus.
• PCIe knowledge: Familiarity with ATS and PRI and their interaction with system-level translation engines.
• Protocol mastery: Knowledge of AMBA protocols, specifically AXI4.
• Object-oriented or functional programming: Proficiency in at least one language (Scala, C++, or Java); experience with Chisel/Scala is highly preferred.
• Hardware design: Advanced proficiency in SystemVerilog or Verilog with emphasis on high-quality, maintainable code.
• Communication: Fluent English with ability to document complex microarchitectural specifications clearly.
• Education: MS/PhD in EE, CE, or related technical discipline.

Additional Information

This position requires a successful background and reference checks and satisfactory proof of your right to work in France. Any offer is contingent on verification of eligibility to access export-controlled technology under applicable export control laws, or on obtaining any necessary export licenses or approvals. SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.