Senior SoC Systems Design & RTL Verification Engineer

Qualcomm; Provence-Alpes-Côte d'Azur; On-site; EUR 75,000 - 110,000; Full time

Job summary

Qualcomm France S.A.R.L. seeks an experienced engineer to develop system level platforms for RTL simulation and FPGA emulation.

You will integrate CPUs/NSP and memory controllers in SystemVerilog, and design testbench modules (traffic generators, DDR models) using SystemVerilog or DPI-C in C. Responsibilities include building functional platforms, debugging integrations, and mapping the platform across multiple emulators, with strong focus on verification methodologies and early performance

Qualifications

• Good RTL development skills: SystemVerilog/Verilog integration and design.
• Systems understanding: Bus Protocols, DDR, SOC.
• Emulation methodologies knowledge.

Responsibilities

• Build and maintain system level platforms for RTL simulation and FPGA Emulation.
• Integrate CPUs/NSP and infrastructure IPs in SystemVerilog (and DPI-C).
• Design RTL testbench modules such as traffic generators or DDR memory models in SystemVerilog/C.
• Provide functional platforms by running and debugging integration and system level testcases.
• Map the full platform on various Emulators.

Skills

SystemVerilog

C

C++

Python

Education

Micro-electronics or similar Engineer Diploma

Bachelor's degree in Science, Engineering, or related field

Master's degree in Science, Engineering, or related field

PhD in Science, Engineering, or related field

Tools

ModelSim

Linux

Job description

Qualcomm France S.A.R.L. seeks an experienced engineer to develop system level platforms for RTL simulation and FPGA emulation.

You will integrate CPUs/NSP and memory controllers in SystemVerilog, and design testbench modules (traffic generators, DDR models) using SystemVerilog or DPI-C in C. Responsibilities include building functional platforms, debugging integrations, and mapping the platform across multiple emulators, with strong focus on verification methodologies and early performance