ASIC/FPGA Design Engineer – RTL, SoC & Verification

Menta SAS; Valbonne; In loco; EUR 40.000 - 70.000; Tempo pieno

Descrizione del lavoro

Menta SAS is seeking talented engineers to join our Sophia-Antipolis team to work on large SoC designs, RTL verification, and FPGA porting.

You will draft specifications, perform architectural studies, integrate with cross‑team partners, and contribute to board bring‑up and debugging. We offer a challenging, creative environment with strong learning opportunities as the company grows, and opportunities for career advancement.

Competenze

• 1–3+ years of engineering experience.
• RTL and testbench development with Verilog, SystemVerilog or VHDL.
• Familiarity with SoC architectures and interconnects e.g. AXI, AHB.
• Knowledge of at least one full ASIC or FPGA implementation flow.
• Excellent spoken and written English.

Mansioni

• RTL design, verification and validation.
• Architectural studies, writing specifications.
• Porting to FPGA, implementation and optimization.
• Board bring-up and debugging.
• Cross-team collaboration.
• Provide technical support to customers and partners.

Conoscenze

RTL design

Verilog/VHDL

SoC architectures

ASIC/FPGA flow

Verification methods

Git

Scripting

English

Cross-team collaboration

Descrizione del lavoro

Menta SAS is seeking talented engineers to join our Sophia-Antipolis team to work on large SoC designs, RTL verification, and FPGA porting.

You will draft specifications, perform architectural studies, integrate with cross‑team partners, and contribute to board bring‑up and debugging. We offer a challenging, creative environment with strong learning opportunities as the company grows, and opportunities for career advancement.