Junior ASIC Design Engineer — SoC & eFPGA (France)

IC Resources; Provence-Alpes-Côte d'Azur; On-site; EUR 42,000 - 64,000; Full time

Job summary

IC Resources is seeking a Junior ASIC Design Engineer for Sophia Antipolis, France. This early-career role offers hands-on experience across the full digital design lifecycle, from RTL to board bring-up, in a collaborative semiconductor team.

You will work on SoC designs, contribute to FPGA/ASIC flows, verify designs using Verilog, SystemVerilog or VHDL, and develop skills across multiple disciplines while living on the French Riviera.

Qualifications

• 1-3 years of ASIC, FPGA or digital design experience.
• Experience with Verilog, SystemVerilog or VHDL.
• Understanding of SoC architectures and protocols such as AXI or AHB.
• Knowledge of ASIC or FPGA implementation flows.
• Experience with verification, scripting and version control.

Responsibilities

• RTL design and verification using Verilog, SystemVerilog or VHDL.
• SoC architecture, design specifications and block ownership.
• FPGA implementation, optimisation and prototyping.
• Hardware validation, board bring-up and debugging.
• Collaboration with experienced engineers across multiple disciplines.

Job description

IC Resources is seeking a Junior ASIC Design Engineer for Sophia Antipolis, France. This early-career role offers hands-on experience across the full digital design lifecycle, from RTL to board bring-up, in a collaborative semiconductor team.

You will work on SoC designs, contribute to FPGA/ASIC flows, verify designs using Verilog, SystemVerilog or VHDL, and develop skills across multiple disciplines while living on the French Riviera.