Junior ASIC/FPGA Design Engineer – SoC & eFPGA, France

Intellectual Capital Resources Ltd; Provence-Alpes-Côte d'Azur; On-site; EUR 42,000 - 56,000; Full time

Job summary

Intellectual Capital Resources Ltd in Sophia Antipolis, France, is seeking a Junior ASIC Design Engineer to contribute to innovative embedded FPGA (eFPGA) technology and full‑lifecycle digital design.

You will work on RTL/SoC design, verify modules, and collaborate with experienced engineers across disciplines while gaining hands-on experience and taking ownership early in a growing semiconductor team near the Mediterranean coast.

Qualifications

• 1–3 years of ASIC, FPGA or digital design experience.
• Experience with Verilog, SystemVerilog or VHDL.
• Understanding of SoC architectures and protocols such as AXI or AHB.
• Knowledge of ASIC or FPGA implementation flows.
• Experience with verification, scripting and version control.

Responsibilities

• RTL design and verification using Verilog, SystemVerilog or VHDL.
• SoC architecture, design specifications and block ownership.
• FPGA implementation, optimisation and prototyping.
• Hardware validation, board bring-up and debugging.
• Collaboration with experienced engineers across multiple disciplines.

Skills

RTL design

SoC architectures

Verification & scripting

Tools

Verilog

SystemVerilog

VHDL

Job description

Intellectual Capital Resources Ltd in Sophia Antipolis, France, is seeking a Junior ASIC Design Engineer to contribute to innovative embedded FPGA (eFPGA) technology and full‑lifecycle digital design.

You will work on RTL/SoC design, verify modules, and collaborate with experienced engineers across disciplines while gaining hands-on experience and taking ownership early in a growing semiconductor team near the Mediterranean coast.