Junior ASIC Design Engineer

IC Resources; Provence-Alpes-Côte d'Azur; On-site; EUR 42,000 - 56,000; Full time

Job summary

Intellectual Capital Resources Ltd in Sophia Antipolis, France, is seeking a Junior ASIC Design Engineer to contribute to innovative embedded FPGA (eFPGA) technology and full‑lifecycle digital design.

You will work on RTL/SoC design, verify modules, and collaborate with experienced engineers across disciplines while gaining hands-on experience and taking ownership early in a growing semiconductor team near the Mediterranean coast.

Qualifications

• 1–3 years of ASIC, FPGA or digital design experience.
• Experience with Verilog, SystemVerilog or VHDL.
• Understanding of SoC architectures and protocols such as AXI or AHB.
• Knowledge of ASIC or FPGA implementation flows.
• Experience with verification, scripting and version control.

Responsibilities

• RTL design and verification using Verilog, SystemVerilog or VHDL.
• SoC architecture, design specifications and block ownership.
• FPGA implementation, optimisation and prototyping.
• Hardware validation, board bring-up and debugging.
• Collaboration with experienced engineers across multiple disciplines.

Skills

RTL design

SoC architectures

Verification & scripting

Tools

Verilog

SystemVerilog

VHDL

Job description

Junior ASIC Design Engineer – Sophia Antipolis, France

Location: Sophia Antipolis, FranceExperience: 1–3 years Industry: Semiconductors | ASIC | FPGA | RTL Design

An exciting opportunity for a Junior ASIC Design Engineer to join a growing semiconductor company developing innovative embedded FPGA (eFPGA) technology in Sophia Antipolis, on the French Riviera.

This is a fantastic opportunity for an early-career engineer looking to gain hands-on experience across the full digital design lifecycle, take ownership of their work and develop alongside a growing engineering team.

You’ll work on complex System-on-Chip (SoC) designs, contributing to both internal products and customer projects.

Responsibilities

• RTL design and verification using Verilog, SystemVerilog or VHDL.
• SoC architecture, design specifications and block ownership.
• FPGA implementation, optimisation and prototyping.
• Hardware validation, board bring-up and debugging.
• Collaboration with experienced engineers across multiple disciplines.

Requirements

• 1–3 years of ASIC, FPGA or digital design experience.
• Experience with Verilog, SystemVerilog or VHDL.
• Understanding of SoC architectures and protocols such as AXI or AHB.
• Knowledge of ASIC or FPGA implementation flows.
• Experience with verification, scripting and version control.

Why apply?

Join a growing semiconductor company where your contributions will be visible, you’ll have the opportunity to take on responsibility early and develop your technical skills across a variety of projects. All while living and working in Sophia Antipolis, just 15 minutes from the Mediterranean coast, surrounded by some of the most beautiful scenery in southern France.

Applicants must already have the right to work in France. Visa sponsorship is not available.