Application Specific Integrated Circuit Design Engineer

Menta SAS; Valbonne; On-site; EUR 40,000 - 70,000; Full time

Job summary

Menta SAS is seeking talented engineers to join our Sophia-Antipolis team to work on large SoC designs, RTL verification, and FPGA porting.

You will draft specifications, perform architectural studies, integrate with cross‑team partners, and contribute to board bring‑up and debugging. We offer a challenging, creative environment with strong learning opportunities as the company grows, and opportunities for career advancement.

Qualifications

• 1–3+ years of engineering experience.
• RTL and testbench development with Verilog, SystemVerilog or VHDL.
• Familiarity with SoC architectures and interconnects e.g. AXI, AHB.
• Knowledge of at least one full ASIC or FPGA implementation flow.
• Excellent spoken and written English.

Responsibilities

• RTL design, verification and validation.
• Architectural studies, writing specifications.
• Porting to FPGA, implementation and optimization.
• Board bring-up and debugging.
• Cross-team collaboration.
• Provide technical support to customers and partners.

Skills

RTL design

Verilog/VHDL

SoC architectures

ASIC/FPGA flow

Verification methods

Git

Scripting

English

Cross-team collaboration

Job description

Menta is a privately-held company, the world leader in disruptive reprogrammable embedded FPGA. We are a fast-growing company located in one of the most beautiful high-tech places in Europe: Sophia-Antipolis business park (15mn from the Mediterranean sea, 30mn from mountains). Our region offers an unmatched environment for balancing work, family life, sports, nature and many other activities.

As Menta embarks on the expansion phase, we are actively seeking talented engineers to join our teams dedicated to new project development. Successful candidates will work on large System-on-Chip (SoC) designs, encompassing both internal products and customer-driven projects. Career advancement opportunities are to be expected as the company grows.

Responsibilities

• RTL design, verification and validation
• Architectural studies, writing specifications
• Porting to FPGA, implementation and optimization
• Board bring-up and debugging
• Cross-team collaboration
• Provide technical support to customers and partners

We provide a challenging and creative environment where contributions are highly visible. We encourage you to take initiatives.

We expect our engineers to be energetic and driven to succeed because this is an opportunity to learn a lot and take on many responsibilities. Career advancement opportunities are to be expected as the company grows.

Qualifications

• 1-3 or more years of engineering experience
• RTL and testbench development with Verilog, System Verilog or VHDL
• Familiarity with SoC architectures. System-level data exchange protocols and interconnects: AXI, AHB or similar
• Knowledge of at least one full ASIC or FPGA implementation flow
• Good knowledge of hardware verification methodologies
• Git or similar VCS
• Scripting and flow automation (bash, Tcl or others)
• Excellent spoken and written English
• Team Player capable of cross-team collaboration. Clear communication skills

Nice To Have

• Experience in hardware acceleration of algorithms, tuning, optimization
• Familiarity with static checkers (Lint, CDC, RDC) is big plus
• Behavioral modelling (SystemC, Qemu or similar …)
• High-speed serial interfaces (Ethernet, PCIe, USB or others) is a plus