FPGA Design Engineer for AI Accelerators & SoC

Inria Rennes; Rennes; On-site; EUR 45,000 - 65,000; Full time

Job summary

Inria Rennes, TARAN team, seeks an FPGA hardware design engineer to design and verify complex digital systems using FPGAs for hardware prototypes, including AI accelerators and security-oriented IP. You will participate in the full design flow, from microarchitecture to back-end verification, collaborating with researchers across architecture, verification, and performance analysis.

You will work on implementing FPGA architectures, developing synthesizable RTL, performing timing analysis, and

Qualifications

• Graduated from a University or Engineering School in Computer Science, Computer Engineering or Electronic/Electrical Engineering.
• Solid understanding of SoC/FPGA design methodologies and techniques with hands-on experience for complex SoC
• Experience in RTL design using Verilog, SystemVerilog or VHDL
• Knowledge of at least one full FPGA implementation flow

Responsibilities

• Define FPGA architecture and develop synthesizable RTL (VHDL or SV) for communication protocols, memory controllers and AI accelerators.
• Develop testbenches and simulations to verify designs.
• Perform static timing analysis and timing closure for tight real-time constraints and multiple clock domains.
• Board bring-up, system integration, and debugging with oscilloscopes and analyzers.
• Create and maintain FPGA specifications, timing budgets, and interface definitions.

Skills

SoC/FPGA design

RTL coding (Verilog SV VHDL)

SystemVerilog

VHDL

Back-end design (place & routing)

FPGA implementation flow

Education

Engineering degree in CS/CE/EE

Tools

Placement & routing tools

AMBA protocol (AXI/AHB/CHI)

Job description

Inria Rennes, TARAN team, seeks an FPGA hardware design engineer to design and verify complex digital systems using FPGAs for hardware prototypes, including AI accelerators and security-oriented IP. You will participate in the full design flow, from microarchitecture to back-end verification, collaborating with researchers across architecture, verification, and performance analysis.

You will work on implementing FPGA architectures, developing synthesizable RTL, performing timing analysis, and