EMIR / Power Integrity Engineer

Aion Silicon Ltd; Barcelona; On-site; EUR 90,000 - 120,000; Full time

Job summary

Aion Silicon Ltd is seeking an EMIR / Power Integrity Engineer to join the SoC Physical Design team in Barcelona. You will lead PDN planning, PDN optimization, EMIR verification, and signoff for advanced semiconductor designs.

Responsibilities include IR drop analyses, EM analysis, ECO implementation, and signoff-driven improvements. You will collaborate with PD, CAD, RTL, Package, and Reliability teams and automate flows with Tcl, Python, Perl, or Shell scripting.

Qualifications

• Experience with EMIR signoff methodologies and CAD automation.
• Strong knowledge of PDN, EM, IRDrop, and power integrity.
• Familiarity with packaging parasitics and power delivery architecture.
• Ability to develop signoff methodologies and automation flows.
• Excellent debugging and analytical skills.

Responsibilities

• Perform Power Integrity and EMIR analysis for complex SoC designs.
• Develop, analyze, and optimize PDNs to meet power and reliability targets.
• Execute Static and Dynamic IR Drop and EM analysis across design cycles.
• Define simulation setups and signoff criteria for PI verification.
• Enhance EMIR analysis flows with timing, package, and board abstractions.
• Identify and root-cause EM/IR/EMI violations; implement ECOs.
• Provide ECO solutions to improve power grid, decap insertion, and routing.
• Validate ECO effectiveness via iterative EMIR analysis and signoff closure.
• Collaborate with Physical Design, CAD, RTL, Package, and Reliability teams.
• Automate flows for analysis, debugging, and reporting using scripting.

Skills

EMIR analysis

Power Integrity

PDN design

Scripting

Debugging

Communication

Education

Bachelors/Masters in Electrical Engineering

Tools

Cadence Voltus

Ansys RedHawk/RedHawk-SC

Synopsys PrimeRail/PrimePower

Cadence Innovus

Synopsys ICC2

FC_SHELL

Tcl, Python, Perl, Shell scripting

Job description

We are seeking a skilled EMIR / Power Integrity Engineer to join our SoC Physical Design team. The ideal candidate will be responsible for power delivery network (PDN) planning, power integrity analysis, EMIR verification, and signoff for advanced semiconductor designs. The role involves ensuring reliable power delivery across the chip through static and dynamic IR drop analysis, electromigration verification, power grid optimization, and ECO implementation to achieve signoff-quality designs.

Key Responsibilities

Perform Power Integrity and EMIR analysis for complex SoC, subsystem, and IP designs.

Develop, analyze, and optimize Power Delivery Networks (PDN) to meet performance, power, and reliability requirements.

Execute Static IR Drop, Dynamic IR Drop, and Electromigration (EM) analysis throughout the design cycle.

Define simulation methodologies, run setups, and signoff criteria for power integrity verification.

Develop and enhance CAD-based EMIR analysis flows incorporating timing, package, and board-level abstractions.

Identify, debug, and root-cause EM, Static IR, and Dynamic IR violations.

Provide and implement ECO solutions to resolve power integrity violations, including power grid enhancements, strap optimization, cell spreading, decap insertion, power routing improvements, and layout modifications.

Validate ECO effectiveness through iterative EMIR analysis and drive complete signoff closure.

Collaborate closely with Physical Design, CAD, RTL, Package, and Reliability teams to achieve power integrity goals.

Automate analysis, debugging, and reporting flows using Tcl, Python, Perl, or Shell scripting.

Support advanced technology nodes and contribute to methodology development and continuous improvement.

Required / Preferred Qualifications

Bachelor's or Master's degree in Electrical/Electronics Engineering or related field.

5+ years of ASIC/SoC EMIR experience.

Knowledge of UPF and low-power design methodologies.

Experience developing signoff methodologies and CAD automation flows.

Understanding of package parasitics and power delivery architecture.

Strong analytical, debugging, and communication skills.

Strong understanding of:

Power Delivery Networks (PDN)

Electromigration (EM)

Static and Dynamic IR Drop Analysis

Power Integrity and Reliability Concepts

Familiarity with Physical Design flow including Floorplanning, Placement, CTS, Routing, and Signoff.

Experience with advanced technology nodes (7nm, 5nm, 3nm, or below).

Strong scripting skills in Tcl, Python, Perl, or Shell.

Tools Required

Cadence Voltus, Ansys RedHawk/RedHawk-SC, Synopsys PrimeRail/PrimePower for EMIR, Static/Dynamic IR Drop analysis, Power Integrity verification, and signoff.

Cadence Innovus / Synopsys ICC2 / FC_SHELL for power grid implementation, ECO execution, decap insertion, and EMIR closure.

Tcl, Python, Perl, and Shell Scripting for flow automation, methodology development, debugging, and reporting.