Senior Hardware Design Engineer (Fpga)

Gmv; Madrid; Híbrido; EUR 70.000 - 100.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Telework 8 weeks

Flexible hours

Career development

Mobility (intl)

Relocation package

Descripción de la vacante

GMV in Madrid is seeking a Senior Hardware Design Engineer (FPGA) to lead FPGA/SoC hardware architecture and system optimization within the space sector.

You will mentor junior engineers, collaborate across locations, and drive HDL coding, advanced verification (SystemVerilog/UVM), and documentation.

This role offers telework a portion of the year, flexible hours, international mobility and a path for technical leadership.

Formación

• Experience in FPGA/SoC architecture and HDL coding.
• Advanced verification using SystemVerilog/UVM.
• Ability to produce technical documentation.
• Willingness to travel within Europe.
• Mentoring and coaching teammates.

Responsabilidades

• Define architecture for FPGA/SoC hardware and interfaces.
• Code in VHDL/Verilog.
• Perform advanced verification using SystemVerilog/UVM.
• Optimize resources, timing and power.
• Produce technical documentation for hardware.
• Mentor and coach junior engineers.
• Collaborate across locations to ensure system-level optimization.

Conocimientos

FPGA architecture

HDL coding

SystemVerilog/UVM

C++/Python

Mentoring

Team collaboration

Effective communication

Herramientas

Vivado

Quartus

ModelSim

QuestaSim

Descripción del empleo

In this role you will lead FPGA/SoC hardware design projects within GMV’s space sector, driving architecture definition and system optimization. You will work closely with a cross-functional team, mentoring junior engineers and shaping critical hardware solutions. Expect hands-on work with architecture, HDL coding, and advanced verification to meet stringent performance and reliability needs. You will collaborate across locations, contributing to system-level optimization and documentation. This is an opportunity to influence high-impact space hardware and grow as a technical leader.

• 8 weeks teleworking per year
• Flexible start/finish times
• Career plan development, training and language learning support
• National and international mobility
• Relocation package
• Define architecture for FPGA/SoC hardware
• Code in VHDL/Verilog
• Perform advanced verification using SystemVerilog/UVM
• Optimize resources and timing
• Define HW/SW interfaces
• Produce technical documentation
• Advanced VHDL/Verilog, synthesis and verification tools (Vivado, Quartus, ModelSim, QuestaSim)
• Modular/IP design, timing optimization, high-speed interfaces
• C++ or Rust, Python, Git
• Knowledge of Process Automation, signal processing, HDL coder, soft core processors, DO-254, ECSS
• ASIC design would be an asset
• Willingness to travel within Europe
• mentoring and coaching
• team collaboration
• effective communication
• VHDL
• SystemVerilog/UVM

Senior Hardware Design Engineer (FPGA) tres cantos, madrid, es