Fpga Contractor - Systemverilog

Vivid Resourcing; Madrid; Híbrido; EUR 83.000 - 138.000; A tiempo parcial

Descripción de la vacante

Vivid Resourcing is seeking a Senior FPGA Engineer for a Barcelona-based project, collaborating with a global R&D team to design, verify and deliver FPGA functionality.

The role emphasizes hands-on SystemVerilog development for multi-FPGA systems, including verification, integration across hardware, firmware and software, with on-site presence 1–2 days per week in Barcelona.

Formación

• Good experience in FPGA design and development using SystemVerilog.
• Hands-on experience building FPGA functionality for multi-FPGA or complex FPGA-based systems.
• Solid grounding in digital design fundamentals — clock domain crossing (CDC), memory architectures, interfaces, and timing analysis.
• Ability to debug and integrate FPGA solutions within larger, complex system architectures.

Responsabilidades

• Design, implement, verify, and maintain FPGA functionality using SystemVerilog. Perform simulation, synthesis, implementation, timing closure, and hardware validation. Debug complex issues across FPGA, firmware, software, and hardware domains.

Conocimientos

SystemVerilog

FPGA design

Multi-FPGA systems

CDC

Digital design fundamentals

Git

Communication

Debugging complex systems

Herramientas

QuestaSim

UVM

Vivado

VHDL

Python/Tcl

CI/CD

Descripción del empleo

This position is only open for freelance/contractor/autonomo model - visa sponsorship is not supported.

For a global customer in Barcelona, we are searching for an FPGA Engineer to design and implement FPGA functionality using SystemVerilog for their synchronization and instrumentation platforms.

Your work will directly power some of the most demanding applications in the world today, including quantum computing, 6G, radar, and large-scale test systems. This is a hands‑on FPGA development and product implementation role centered on multi-FPGA systems — not an ASIC design position.

You'll join a highly collaborative, globally distributed R&D organization, working alongside software, hardware, and systems engineers to develop, integrate, verify, and release FPGA technology that ships inside commercial products used by engineers around the world.

Responsibilities

• Design, implement, verify, and maintain FPGA functionality using SystemVerilog. Perform simulation, synthesis, implementation, timing closure, and hardware validation. Debug complex issues across FPGA, firmware, software, and hardware domains.

Qualifications

• Good experience in FPGA design and development using SystemVerilog. Hands‑on experience building FPGA functionality for multi‑FPGA or complex FPGA‑based systems. Proven track record with FPGA simulation, synthesis, implementation, and timing closure. Solid grounding in digital design fundamentals — clock domain crossing (CDC), memory architectures, interfaces, and timing analysis. Ability to debug and integrate FPGA solutions within larger, complex system architectures. Comfort with modern version control (Git) workflows, including branching, code reviews, and merge management. Strong communication skills and a collaborative, team‑first mindset.

Nice to Have

• Experience with QuestaSim, UVM, or other advanced FPGA verification methodologies. Experience with Xilinx FPGA devices and Vivado. Familiarity with VHDL and mixed‑language FPGA projects. Knowledge of high‑speed interfaces such as PCIe, Ethernet, or JESD204. Background in test and measurement systems. Scripting skills in Python, Tcl, or C++. Exposure to CI/CD pipelines and automated testing workflows.

Additional Details

• SENIORITY: Senior
• START DATE: October
• DURATION: 6 Months
• EXTENSION: Yes
• CONTRACT: Freelance
• LOCATION: Barcelona
• ONSITE POLICY: 1-2 days per week
• HOURS PER WEEK: 40
• LANGUAGES: Fluent English
• INTERVIEW PROCESS: 1-2 stages