Asic Design Engineer - Tres Cantos

Gmv; Madrid; Híbrido; EUR 55.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Telework 8 weeks/yr

Flexible hours

Fridays/Summer hours

Language learning support

Descripción de la vacante

GMV is seeking an experienced hardware engineer to contribute to receiver technology projects. You will migrate architectures from Xilinx MPSoC/FPGA to ASIC, shaping the target architecture, implementing RTL blocks, and optimizing interfaces while supporting verification and the overall ASIC flow.

In this hands-on role, you will work within the GMV Receivers team on R&D-driven efforts to deliver new ASIC-based capabilities.

Formación

• Digital RTL design knowledge
• Understanding of FPGA/SoC/MPSoC architectures
• Experience with internal buses, IP integration and functional verification
• ASIC flow experience including simulation and synthesis tools
• SystemVerilog, UVM, assertions or cocotb for verification
• Embedded ARM/RISC-V and hardware/software partitioning
• Experience with industry tools (Synopsys, Cadence, Siemens EDA, Vivado or Vitis)
• VHDL and FPGA background

Responsabilidades

• Define and evolve the target ASIC architecture
• Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog)
• Analyze and optimize internal interfaces (buses, memories, clocks, resets)
• Participate in functional verification, simulation, and debugging
• Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, design closure
• Document architecture decisions and validation results

Conocimientos

Embedded ARM/RISC-V experience

Hardware/software partitioning

Functional verification

SystemVerilog/UVM

RTL design

Verilog/VHDL

Team collaboration

Educación

Bachelor's degree in Electrical Engineering or related field

Herramientas

Vivado

Synopsys

Cadence

Vitis

Siemens EDA

Descripción del empleo

In this role you will contribute to receiver technology projects, focusing on migrating an architecture from Xilinx MPSoC/FPGA to an ASIC solution. You will shape the target ASIC architecture, implement RTL blocks, and optimize internal interfaces while supporting verification and the overall ASIC flow. You’ll work within the GMV Receivers team on R&D-driven efforts that aim to deliver new ASIC-based capabilities. This is a hands-on, impact-oriented opportunity at the intersection of hardware architecture and RTL development.

• 8 weeks per year teleworking
• Flexible start/finish times
• Intensive Fridays and summer hours
• language learning support in-house training
• Define and evolve the target ASIC architecture
• Develop and adapt RTL blocks (VHDL/Verilog/SystemVerilog)
• Analyze and optimize internal interfaces (buses, memories, synchronization, clocks, resets)
• Participate in functional verification, simulation, and design debugging
• Contribute to the ASIC flow: synthesis, timing analysis, CDC/RDC, DFT, and design closure
• Document architecture, decisions, and validation results
• digital RTL design knowledge
• FPGA, SoC or MPSoC architectures understanding
• internal buses, IP integration, and functional verification experience
• ASIC flow experience including simulation and synthesis tools
• SystemVerilog, UVM, assertions or cocotb (verification)
• embedded ARM/RISC-V and hardware/software partitioning
• experience with Synopsys, Cadence, Siemens EDA, Vivado, or Vitis tools
• VHDL
• FPGA