Fpga Engineer (Systemverilog)

Vivid Resourcing; Barcelona; Presencial; EUR 96.000 - 165.000; A tiempo parcial

Descripción de la vacante

Vivid Resourcing busca en Barcelona un/a freelance (autónomo) Senior/Experto en desarrollo FPGA para diseñar e implementar funcionalidades en SystemVerilog en plataformas de sincronización e instrumentación. Trabajarás en sistemas FPGA multi‑chip y colaborarás con equipos de software, hardware y sistemas para entregar tecnología de FPGA que alimenta productos comerciales.

El puesto es práctico, orientado a producto, con una organización de I+D global y distribución.

Formación

• Titulación universitaria en Ingeniería Eléctrica, Ingeniería Informática o campo relacionado.
• Experiencia demostrada en diseño y desarrollo de FPGA con SystemVerilog.
• Experiencia en entornos multi‑FPGA y sistemas complejos de FPGA.
• Experiencia en simulación, síntesis, implementación y temporización de FPGA.
• Conocimientos de dispositivos Xilinx y Vivado.
• Base sólida en diseño digital: CDC, arquitecturas de memoria e interfaces.

Responsabilidades

• Diseñar, implementar, verificar y mantener funcionalidades de FPGA con SystemVerilog. Realizar simulación, síntesis, implementación, temporización y validación de hardware.
• Depurar problemas complejos entre FPGA, firmware, software y hardware.
• Colaborar en entornos de equipo y flujos de trabajo con control de versiones (Git).
• Participar en la verificación y validación de soluciones FPGA dentro de sistemas grandes.

Conocimientos

SystemVerilog

FPGA design

Multi-FPGA systems

Cross-domain debugging

Git workflows

Educación

BS/MS/PhD in Electrical Engineering, Computer Engineering or Computer Science

Herramientas

Vivado

QuestaSim

UVM

VHDL

Descripción del empleo

Descripción del trabajo

For a global customer in Barcelona, we are searching for a freelance (autonomo) Senior/Expert FPGA Development Engineer to design and implement FPGA functionality using SystemVerilog for their synchronization and instrumentation platforms. Your work will directly power some of the most demanding applications in the world today, including quantum computing, 6G, radar, and large-scale test systems. This is a hands‑on FPGA development and product implementation role centered on multi‑FPGA systems — not an ASIC design position. You'll join a highly collaborative, globally distributed R&D organization, working alongside software, hardware, and systems engineers to develop, integrate, verify, and release FPGA technology that ships inside commercial products used by engineers around the world.

Responsibilities

• Design, implement, verify, and maintain FPGA functionality using SystemVerilog. Perform simulation, synthesis, implementation, timing closure, and hardware validation. Debug complex issues across FPGA, firmware, software, and hardware domains.

Qualifications

• BS/MS/PhD in Electrical Engineering, Computer Engineering, Computer Science, or a related field. Strong professional experience in FPGA design and development using SystemVerilog. Hands‑on experience building FPGA functionality for multi‑FPGA or complex FPGA‑based systems. Proven track record with FPGA simulation, synthesis, implementation, and timing closure. Experience with Xilinx FPGA devices and Vivado. Solid grounding in digital design fundamentals — clock domain crossing (CDC), memory architectures, interfaces, and timing analysis. Ability to debug and integrate FPGA solutions within larger, complex system architectures. Comfort with modern version control (Git) workflows, including branching, code reviews, and merge management. Strong communication skills and a collaborative, team‑first mindset.

Nice to Have

• Experience with QuestaSim, UVM, or other advanced FPGA verification methodologies. Familiarity with VHDL and mixed-language FPGA projects. Knowledge of high‑speed interfaces such as PCIe, Ethernet, or JESD204. Background in test and measurement systems. Scripting skills in Python, Tcl, or C++. Exposure to CI/CD pipelines and automated testing workflows.

Additional Details

SENIORITY: Senior START DATE: September DURATION: 6 Months EXTENSION: Yes CONTRACT: Freelance LOCATION: Barcelona ONSITE POLICY: 2‑3 days per week HOURS PER WEEK: 40 LANGUAGES: Fluent English INTERVIEW PROCESS: 1-2 stages