Senior FPGA Design Engineer – Hybrid, Relocation

GMV; Tres Cantos; Híbrido; EUR 60.000 - 90.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Hybrid working model

Teleworking up to 8 weeks/year

Relocation package

Health, dental and accident insurance

Language learning support

National and international mobility

Descripción de la vacante

GMV in Madrid is seeking a Senior Hardware Design Engineer specializing in FPGA/SoC. You will lead FPGA development, architecture definition, and mentor junior engineers in a fast‑paced environment.

You will work in a hybrid model with some travel across Europe for tests and meetings. Proficiency in VHDL/Verilog, SystemVerilog/UVM, and FPGA toolchains is required, with coding in C++ or Rust and Python beneficial.

Formación

• Experience in FPGA development and architecture definition.
• Proficiency in VHDL/Verilog and FPGA verification tools.
• Familiarity with modular/IP design and timing optimization.

Responsabilidades

• Lead FPGA/SoC hardware design projects and architecture definition.
• Mentor junior engineers and provide technical guidance.
• Define HW/SW interfaces and perform optimization and documentation.

Conocimientos

FPGA development

VHDL/Verilog

SystemVerilog/UVM

C++/Rust

Python

GIT

Herramientas

Vivado

Quartus

ModelSim

QuestaSim

Descripción del empleo

GMV in Madrid is seeking a Senior Hardware Design Engineer specializing in FPGA/SoC. You will lead FPGA development, architecture definition, and mentor junior engineers in a fast‑paced environment.

You will work in a hybrid model with some travel across Europe for tests and meetings. Proficiency in VHDL/Verilog, SystemVerilog/UVM, and FPGA toolchains is required, with coding in C++ or Rust and Python beneficial.